threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
43 lines
1.6 KiB
JSON
43 lines
1.6 KiB
JSON
[
|
|
{
|
|
"EventCode": "0x5C",
|
|
"UMask": "0x1",
|
|
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
|
|
"Counter": "0,1,2,3",
|
|
"EventName": "CPL_CYCLES.RING0",
|
|
"PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
|
|
"SampleAfterValue": "2000003",
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
|
},
|
|
{
|
|
"EventCode": "0x5C",
|
|
"UMask": "0x2",
|
|
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
|
|
"Counter": "0,1,2,3",
|
|
"EventName": "CPL_CYCLES.RING123",
|
|
"PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
|
|
"SampleAfterValue": "2000003",
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
|
},
|
|
{
|
|
"EdgeDetect": "1",
|
|
"EventCode": "0x5C",
|
|
"UMask": "0x1",
|
|
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
|
|
"Counter": "0,1,2,3",
|
|
"EventName": "CPL_CYCLES.RING0_TRANS",
|
|
"CounterMask": "1",
|
|
"SampleAfterValue": "100003",
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
|
},
|
|
{
|
|
"EventCode": "0x63",
|
|
"UMask": "0x1",
|
|
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
|
|
"Counter": "0,1,2,3",
|
|
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
|
|
"PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
|
|
"SampleAfterValue": "2000003",
|
|
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
|
}
|
|
] |