threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
133 lines
5.1 KiB
C
133 lines
5.1 KiB
C
/*
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* Copyright (C) 2015 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __EINT_H
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#define __EINT_H
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/*
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* Hardware registers and settings.
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*/
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#define EINT_STA_BASE (((unsigned long)EINT_BASE + 0x000))
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#define EINT_INTACK_BASE (((unsigned long)EINT_BASE + 0x040))
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#define EINT_MASK_BASE (((unsigned long)EINT_BASE + 0x080))
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#define EINT_MASK_SET_BASE (((unsigned long)EINT_BASE + 0x0c0))
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#define EINT_MASK_CLR_BASE (((unsigned long)EINT_BASE + 0x100))
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#define EINT_SENS_BASE (((unsigned long)EINT_BASE + 0x140))
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#define EINT_SENS_SET_BASE (((unsigned long)EINT_BASE + 0x180))
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#define EINT_SENS_CLR_BASE (((unsigned long)EINT_BASE + 0x1c0))
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#define EINT_SOFT_BASE (((unsigned long)EINT_BASE + 0x200))
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#define EINT_SOFT_SET_BASE (((unsigned long)EINT_BASE + 0x240))
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#define EINT_SOFT_CLR_BASE (((unsigned long)EINT_BASE + 0x280))
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#define EINT_POL_BASE (((unsigned long)EINT_BASE + 0x300))
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#define EINT_POL_SET_BASE (((unsigned long)EINT_BASE + 0x340))
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#define EINT_POL_CLR_BASE (((unsigned long)EINT_BASE + 0x380))
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#define EINT_D0_EN_BASE (((unsigned long)EINT_BASE + 0x400))
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#define EINT_D1_EN_BASE (((unsigned long)EINT_BASE + 0x420))
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#define EINT_D2_EN_BASE (((unsigned long)EINT_BASE + 0x440))
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#define EINT_DBNC_BASE (((unsigned long)EINT_BASE + 0x500))
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#define EINT_DBNC_SET_BASE (((unsigned long)EINT_BASE + 0x600))
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#define EINT_DBNC_CLR_BASE (((unsigned long)EINT_BASE + 0x700))
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#define DEINT_CON_BASE (((unsigned long)EINT_BASE + 0x800))
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#define DEINT_SEL_BASE (((unsigned long)EINT_BASE + 0x840))
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#define DEINT_SEL_SET_BASE (((unsigned long)EINT_BASE + 0x880))
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#define DEINT_SEL_CLR_BASE (((unsigned long)EINT_BASE + 0x8c0))
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#define EINT_EEVT_BASE (((unsigned long)EINT_BASE + 0x900))
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#define EINT_RAW_STA_BASE (((unsigned long)EINT_BASE + 0xA00))
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#define EINT_EMUL_BASE (((unsigned long)EINT_BASE + 0xF00))
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#define SECURE_DIR_EINT_EN (((unsigned long)EINT_BASE + 0xB10))
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#define EINT_DBNC_SET_DBNC_BITS (4)
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#define EINT_DBNC_CLR_DBNC_BITS (4)
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#define EINT_DBNC_SET_EN_BITS (0)
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#define EINT_DBNC_CLR_EN_BITS (0)
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#define EINT_DBNC_SET_RST_BITS (1)
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#define EINT_DBNC_EN_BIT (0x1)
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#define EINT_DBNC_RST_BIT (0x1)
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#define EINT_DBNC_0_MS (0x7)
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#define EINT_DBNC (0xF)
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#define EINT_DBNC_SET_EN (0x1)
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#define EINT_DBNC_CLR_EN (0x1)
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#define EINT_STA_DEFAULT 0x00000000
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#define EINT_INTACK_DEFAULT 0x00000000
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#define EINT_EEVT_DEFAULT 0x00000001
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#define EINT_MASK_DEFAULT 0x00000000
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#define EINT_MASK_SET_DEFAULT 0x00000000
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#define EINT_MASK_CLR_DEFAULT 0x00000000
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#define EINT_SENS_DEFAULT 0x0000FFFF
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#define EINT_SENS_SET_DEFAULT 0x00000000
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#define EINT_SENS_CLR_DEFAULT 0x00000000
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#define EINT_D0EN_DEFAULT 0x00000000
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#define EINT_D1EN_DEFAULT 0x00000000
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#define EINT_D2EN_DEFAULT 0x00000000
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#define EINT_DBNC_DEFAULT(n) 0x00000000
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#define DEINT_MASK_DEFAULT 0x00000000
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#define DEINT_MASK_SET_DEFAULT 0x00000000
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#define DEINT_MASK_CLR_DEFAULT 0x00000000
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/*
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* Define constants.
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*/
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#define MT_EINT_POL_NEG 0
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#define MT_EINT_POL_POS 1
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#define EINTF_TRIGGER_RISING 0x00000001
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#define EINTF_TRIGGER_FALLING 0x00000002
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#define EINTF_TRIGGER_HIGH 0x00000004
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#define EINTF_TRIGGER_LOW 0x00000008
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#define EINT_IRQ(eint) (eint+EINT_IRQ_BASE)
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#define DEMUX_EINT_IRQ(irq) (irq-EINT_IRQ_BASE)
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#define EINT_GPIO(eint) eint
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#define GPIOPIN 0
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#define DEBOUNCE 1
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#define EINT_DELAY_WARNING 3000000
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#define MT_EDGE_SENSITIVE 0
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#define MT_LEVEL_SENSITIVE 1
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#define MT_POLARITY_LOW 0
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#define MT_POLARITY_HIGH 1
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/*
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* Define function prototypes.
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*/
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extern void _print_status(void);
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extern int mt_gpio_set_debounce(unsigned int gpio, unsigned int debounce);
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extern unsigned int mt_gpio_to_eint(unsigned int gpio);
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extern unsigned int mt_gpio_to_irq(unsigned int gpio);
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extern int mt_get_supported_irq_num_ex(void);
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void mt_eint_mask(unsigned int eint_num);
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void mt_eint_unmask(unsigned int eint_num);
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void mt_eint_set_hw_debounce(unsigned int eint_num, unsigned int us);
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void mt_eint_set_polarity(unsigned int eint_num, unsigned int pol);
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unsigned int mt_eint_set_sens(unsigned int eint_num, unsigned int sens);
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void mt_eint_virq_soft_clr(unsigned int virq);
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extern void dump_eint_trigger_history(void);
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/* used to access the gic device tree resource */
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extern int mt_get_supported_irq_num(void);
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/*
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* Define structure prototypes
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*/
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struct EINT_HEADER {
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unsigned int is_autounmask;
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};
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struct pin_node {
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struct rb_node node;
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u32 gpio_pin;
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u32 eint_pin;
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};
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#ifdef CONFIG_MTK_GPIOLIB_STAND
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extern int mtk_pinctrl_get_gpio_mode_for_eint(int pin);
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extern int mtk_pctrl_get_gpio_chip_base(void);
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#endif
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#endif
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