threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
35 lines
1.2 KiB
C
35 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _CAN_PLATFORM_CC770_H
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#define _CAN_PLATFORM_CC770_H
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/* CPU Interface Register (0x02) */
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#define CPUIF_CEN 0x01 /* Clock Out Enable */
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#define CPUIF_MUX 0x04 /* Multiplex */
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#define CPUIF_SLP 0x08 /* Sleep */
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#define CPUIF_PWD 0x10 /* Power Down Mode */
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#define CPUIF_DMC 0x20 /* Divide Memory Clock */
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#define CPUIF_DSC 0x40 /* Divide System Clock */
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#define CPUIF_RST 0x80 /* Hardware Reset Status */
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/* Clock Out Register (0x1f) */
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#define CLKOUT_CD_MASK 0x0f /* Clock Divider mask */
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#define CLKOUT_SL_MASK 0x30 /* Slew Rate mask */
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#define CLKOUT_SL_SHIFT 4
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/* Bus Configuration Register (0x2f) */
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#define BUSCFG_DR0 0x01 /* Disconnect RX0 Input / Select RX input */
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#define BUSCFG_DR1 0x02 /* Disconnect RX1 Input / Silent mode */
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#define BUSCFG_DT1 0x08 /* Disconnect TX1 Output */
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#define BUSCFG_POL 0x20 /* Polarity dominant or recessive */
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#define BUSCFG_CBY 0x40 /* Input Comparator Bypass */
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struct cc770_platform_data {
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u32 osc_freq; /* CAN bus oscillator frequency in Hz */
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u8 cir; /* CPU Interface Register */
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u8 cor; /* Clock Out Register */
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u8 bcr; /* Bus Configuration Register */
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};
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#endif /* !_CAN_PLATFORM_CC770_H */
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