threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
98 lines
2.4 KiB
C
98 lines
2.4 KiB
C
/*
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* Copyright (C) 2019 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#include <linux/types.h>
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#ifndef _HL7005_SW_H_
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#define _HL7005_SW_H_
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#define HL7005_CON0 0x00
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#define HL7005_CON1 0x01
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#define HL7005_CON2 0x02
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#define HL7005_CON3 0x03
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#define HL7005_CON4 0x04
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#define HL7005_CON5 0x05
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#define HL7005_CON6 0x06
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#define HL7005_REG_NUM 7
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/* CON0 */
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#define CON0_TMR_RST_MASK 0x01
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#define CON0_TMR_RST_SHIFT 7
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#define CON0_OTG_MASK 0x01
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#define CON0_OTG_SHIFT 7
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#define CON0_EN_STAT_MASK 0x01
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#define CON0_EN_STAT_SHIFT 6
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#define CON0_STAT_MASK 0x03
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#define CON0_STAT_SHIFT 4
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#define CON0_BOOST_MASK 0x01
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#define CON0_BOOST_SHIFT 3
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#define CON0_FAULT_MASK 0x07
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#define CON0_FAULT_SHIFT 0
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/* CON1 */
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#define CON1_LIN_LIMIT_MASK 0x03
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#define CON1_LIN_LIMIT_SHIFT 6
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#define CON1_LOW_V_MASK 0x03
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#define CON1_LOW_V_SHIFT 4
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#define CON1_TE_MASK 0x01
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#define CON1_TE_SHIFT 3
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#define CON1_CE_MASK 0x01
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#define CON1_CE_SHIFT 2
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#define CON1_HZ_MODE_MASK 0x01
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#define CON1_HZ_MODE_SHIFT 1
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#define CON1_OPA_MODE_MASK 0x01
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#define CON1_OPA_MODE_SHIFT 0
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/* CON2 */
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#define CON2_OREG_MASK 0x3F
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#define CON2_OREG_SHIFT 2
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#define CON2_OTG_PL_MASK 0x01
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#define CON2_OTG_PL_SHIFT 1
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#define CON2_OTG_EN_MASK 0x01
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#define CON2_OTG_EN_SHIFT 0
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/* CON3 */
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#define CON3_VENDER_CODE_MASK 0x07
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#define CON3_VENDER_CODE_SHIFT 5
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#define CON3_PIN_MASK 0x03
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#define CON3_PIN_SHIFT 3
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#define CON3_REVISION_MASK 0x07
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#define CON3_REVISION_SHIFT 0
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/* CON4 */
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#define CON4_RESET_MASK 0x01
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#define CON4_RESET_SHIFT 7
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#define CON4_I_CHR_MASK 0x07
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#define CON4_I_CHR_SHIFT 4
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#define CON4_I_TERM_MASK 0x07
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#define CON4_I_TERM_SHIFT 0
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/* CON5 */
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#define CON5_DIS_VREG_MASK 0x01
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#define CON5_DIS_VREG_SHIFT 6
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#define CON5_IO_LEVEL_MASK 0x01
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#define CON5_IO_LEVEL_SHIFT 5
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#define CON5_SP_STATUS_MASK 0x01
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#define CON5_SP_STATUS_SHIFT 4
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#define CON5_EN_LEVEL_MASK 0x01
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#define CON5_EN_LEVEL_SHIFT 3
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#define CON5_VSP_MASK 0x07
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#define CON5_VSP_SHIFT 0
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/* CON6 */
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#define CON6_ISAFE_MASK 0x07
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#define CON6_ISAFE_SHIFT 4
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#define CON6_VSAFE_MASK 0x0F
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#define CON6_VSAFE_SHIFT 0
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#endif
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