threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
74 lines
2.0 KiB
C
74 lines
2.0 KiB
C
/*
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* Copyright (C) 2013 BayHub Technology Ltd.
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*
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* Authors: Peter Guo <peter.guo@bayhubtech.com>
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* Adam Lee <adam.lee@canonical.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __SDHCI_PCI_O2MICRO_H
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#define __SDHCI_PCI_O2MICRO_H
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#include "sdhci-pci.h"
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/*
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* O2Micro device IDs
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*/
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#define PCI_DEVICE_ID_O2_SDS0 0x8420
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#define PCI_DEVICE_ID_O2_SDS1 0x8421
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#define PCI_DEVICE_ID_O2_FUJIN2 0x8520
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#define PCI_DEVICE_ID_O2_SEABIRD0 0x8620
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#define PCI_DEVICE_ID_O2_SEABIRD1 0x8621
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/*
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* O2Micro device registers
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*/
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#define O2_SD_MISC_REG5 0x64
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#define O2_SD_LD0_CTRL 0x68
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#define O2_SD_DEV_CTRL 0x88
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#define O2_SD_LOCK_WP 0xD3
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#define O2_SD_TEST_REG 0xD4
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#define O2_SD_FUNC_REG0 0xDC
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#define O2_SD_MULTI_VCC3V 0xEE
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#define O2_SD_CLKREQ 0xEC
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#define O2_SD_CAPS 0xE0
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#define O2_SD_ADMA1 0xE2
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#define O2_SD_ADMA2 0xE7
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#define O2_SD_INF_MOD 0xF1
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#define O2_SD_MISC_CTRL4 0xFC
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#define O2_SD_TUNING_CTRL 0x300
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#define O2_SD_PLL_SETTING 0x304
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#define O2_SD_CLK_SETTING 0x328
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#define O2_SD_CAP_REG2 0x330
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#define O2_SD_CAP_REG0 0x334
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#define O2_SD_UHS1_CAP_SETTING 0x33C
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#define O2_SD_DELAY_CTRL 0x350
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#define O2_SD_UHS2_L1_CTRL 0x35C
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#define O2_SD_FUNC_REG3 0x3E0
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#define O2_SD_FUNC_REG4 0x3E4
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#define O2_SD_LED_ENABLE BIT(6)
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#define O2_SD_FREG0_LEDOFF BIT(13)
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#define O2_SD_FREG4_ENABLE_CLK_SET BIT(22)
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#define O2_SD_VENDOR_SETTING 0x110
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#define O2_SD_VENDOR_SETTING2 0x1C8
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extern int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot);
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extern int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip);
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extern int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip);
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#endif /* __SDHCI_PCI_O2MICRO_H */
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