threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
108 lines
3.7 KiB
C
108 lines
3.7 KiB
C
/*
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* Copyright (C) 2016 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _VPU_DVFS_H_
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#define _VPU_DVFS_H_
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/* ++++++++++++++++++++++++++++++++++*/
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/* |opp_index | vpu frequency | power */
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/* ------------------------------------------*/
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/* | 0 | 700 MHz | 336 mA */
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/* ------------------------------------------*/
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/* | 1 | 624 MHz | 250 mA */
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/* ------------------------------------------*/
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/* | 2 | 606 MHz | 221 mA */
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/* ------------------------------------------*/
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/* | 3 | 594 MHz | 208 mA */
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/* ------------------------------------------*/
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/* | 4 | 560 MHz | 140 mA */
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/* ------------------------------------------*/
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/* | 5 | 525 MHz | 120 mA */
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/* ------------------------------------------*/
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/* | 6 | 450 MHz | 114 mA */
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/* ------------------------------------------*/
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/* | 7 | 416 MHz | 84 mA */
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/* ------------------------------------------*/
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/* | 8 | 364 MHz | 336 mA */
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/* ------------------------------------------*/
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/* | 9 | 312 MHz | 250 mA */
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/* ------------------------------------------*/
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/* | 10 | 273 MHz | 221 mA */
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/* ------------------------------------------*/
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/* | 11 | 208 MHz | 208 mA */
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/* ------------------------------------------*/
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/* | 12 | 137 MHz | 140 mA */
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/* ------------------------------------------*/
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/* | 13 | 104 MHz | 120 mA */
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/* ------------------------------------------*/
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/* | 14 | 52 MHz | 114 mA */
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/* ------------------------------------------*/
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/* | 15 | 26 MHz | 114 mA */
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/* ------------------------------------------*/
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/* ++++++++++++++++++++++++++++++++++*/
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enum VPU_OPP_INDEX {
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VPU_OPP_0 = 0,
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VPU_OPP_1 = 1,
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VPU_OPP_2 = 2,
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VPU_OPP_3 = 3,
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VPU_OPP_4 = 4,
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VPU_OPP_5 = 5,
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VPU_OPP_6 = 6,
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VPU_OPP_7 = 7,
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VPU_OPP_8 = 8,
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VPU_OPP_9 = 9,
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VPU_OPP_10 = 10,
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VPU_OPP_11 = 11,
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VPU_OPP_12 = 12,
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VPU_OPP_NUM
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};
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struct VPU_OPP_INFO {
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enum VPU_OPP_INDEX opp_index;
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int power; /*mW*/
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};
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static const int g_vpu_opp_table[VPU_OPP_NUM] = {
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[VPU_OPP_0] = 700000,
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[VPU_OPP_1] = 624000,
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[VPU_OPP_2] = 606000,
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[VPU_OPP_3] = 594000,
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[VPU_OPP_4] = 560000,
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[VPU_OPP_5] = 525000,
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[VPU_OPP_6] = 450000,
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[VPU_OPP_7] = 416000,
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[VPU_OPP_8] = 364000,
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[VPU_OPP_9] = 312000,
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[VPU_OPP_10] = 273000,
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[VPU_OPP_11] = 208000,
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[VPU_OPP_12] = 137000,
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};
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extern struct VPU_OPP_INFO vpu_power_table[VPU_OPP_NUM];
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extern int32_t vpu_thermal_en_throttle_cb(uint8_t vcore_opp, uint8_t vpu_opp);
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extern int32_t vpu_thermal_dis_throttle_cb(void);
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extern int get_vpu_opp(void);
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extern int get_vpu_dspcore_opp(int core);
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extern int get_vpu_platform_floor_opp(void);
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extern int get_vpu_ceiling_opp(int core);
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extern int get_vpu_opp_to_freq(uint8_t step);
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void vpu_enable_mtcmos(void);
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void vpu_disable_mtcmos(void);
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int get_vpu_init_done(void);
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#endif
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