Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
45 lines
1.4 KiB
C
45 lines
1.4 KiB
C
/*
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* Copyright (C) 2018 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __SMI_PUBLIC_H__
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#define __SMI_PUBLIC_H__
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#if IS_ENABLED(CONFIG_MTK_SMI_EXT)
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#if IS_ENABLED(CONFIG_MACH_MT6885) || IS_ENABLED(CONFIG_MACH_MT6893)
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#include "mt6885/smi_port.h"
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#endif
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enum {
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SMI_LARB0, SMI_LARB1, SMI_LARB2, SMI_LARB3, SMI_LARB4,
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SMI_LARB5, SMI_LARB6, SMI_LARB7, SMI_LARB8, SMI_LARB9,
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SMI_LARB10, SMI_LARB11, SMI_LARB12, SMI_LARB13, SMI_LARB14,
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SMI_LARB15, SMI_LARB16, SMI_LARB17, SMI_LARB18, SMI_LARB19,
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SMI_LARB20,
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};
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bool smi_mm_first_get(void);
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s32 smi_bus_prepare_enable(const u32 id, const char *user);
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s32 smi_bus_disable_unprepare(const u32 id, const char *user);
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s32 smi_debug_bus_hang_detect(const bool gce, const char *user);
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s32 smi_sysram_enable(const u32 master_id, const bool enable, const char *user);
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#else
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#define smi_mm_first_get() (true)
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#define smi_bus_prepare_enable(id, user) (0)
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#define smi_bus_disable_unprepare(id, user) (0)
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#define smi_debug_bus_hang_detect(gce, user) (0)
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#define smi_sysram_enable(master_id, enable, user) (0)
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#endif
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#endif
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