threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
187 lines
6.9 KiB
C
187 lines
6.9 KiB
C
/*
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* Copyright (C) 2017 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#ifndef __SCP_REG_H
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#define __SCP_REG_H
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#define SCP_SEMAPHORE (scpreg.cfg + 0x0018)
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#define SCP_3WAY_SEMAPHORE (scpreg.cfg + 0x001c)
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#define SCP_SCP2SPM_VOL_LV (scpreg.cfg + 0x0020)
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/* SCP to SPM IPC clear */
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#define SCP_TO_SPM_REG (scpreg.cfg + 0x0094)
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#define R_GIPC_IN_SET (scpreg.cfg + 0x0098)
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#define R_GIPC_IN_CLR (scpreg.cfg + 0x009c)
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#define B_GIPC0_SETCLR_0 (1 << 0)
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#define B_GIPC0_SETCLR_1 (1 << 1)
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#define B_GIPC0_SETCLR_2 (1 << 2)
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#define B_GIPC0_SETCLR_3 (1 << 3)
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#define B_GIPC1_SETCLR_0 (1 << 4)
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#define B_GIPC1_SETCLR_1 (1 << 5)
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#define B_GIPC1_SETCLR_2 (1 << 6)
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#define B_GIPC1_SETCLR_3 (1 << 7)
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#define B_GIPC2_SETCLR_0 (1 << 8)
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#define B_GIPC2_SETCLR_1 (1 << 9)
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#define B_GIPC2_SETCLR_2 (1 << 10)
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#define B_GIPC2_SETCLR_3 (1 << 11)
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#define B_GIPC3_SETCLR_0 (1 << 12)
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#define B_GIPC3_SETCLR_1 (1 << 13)
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#define B_GIPC3_SETCLR_2 (1 << 14)
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#define B_GIPC3_SETCLR_3 (1 << 15)
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#define B_GIPC4_SETCLR_0 (1 << 16)
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#define B_GIPC4_SETCLR_1 (1 << 17)
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#define B_GIPC4_SETCLR_2 (1 << 18)
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#define B_GIPC4_SETCLR_3 (1 << 19)
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#define R_CORE0_SW_RSTN_CLR (scpreg.cfg_core0 + 0x0000)
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#define R_CORE0_SW_RSTN_SET (scpreg.cfg_core0 + 0x0004)
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#define R_CORE0_DBG_CTRL (scpreg.cfg_core0 + 0x0010)
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#define M_CORE_TBUF_DBG_SEL (0xfff0ff0f)
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#define S_CORE_TBUF_S (4)
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#define S_CORE_TBUF1_S (16)
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#define R_CORE0_WDT_IRQ (scpreg.cfg_core0 + 0x0030)
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#define B_WDT_IRQ (1 << 0)
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#define R_CORE0_WDT_CFG (scpreg.cfg_core0 + 0x0034)
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#define V_INSTANT_WDT 0x80000000
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#define R_CORE0_STATUS (scpreg.cfg_core0 + 0x0070)
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#define B_CORE_GATED (1 << 0)
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#define B_CORE_HALT (1 << 1)
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#define R_CORE0_MON_PC (scpreg.cfg_core0 + 0x0080)
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#define R_CORE0_MON_LR (scpreg.cfg_core0 + 0x0084)
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#define R_CORE0_MON_SP (scpreg.cfg_core0 + 0x0088)
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#define R_CORE0_TBUF_WPTR (scpreg.cfg_core0 + 0x008c)
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#define R_CORE0_MON_PC_LATCH (scpreg.cfg_core0 + 0x00d0)
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#define R_CORE0_MON_LR_LATCH (scpreg.cfg_core0 + 0x00d4)
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#define R_CORE0_MON_SP_LATCH (scpreg.cfg_core0 + 0x00d8)
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#define R_CORE0_T1_MON_PC (scpreg.cfg_core0 + 0x0160)
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#define R_CORE0_T1_MON_LR (scpreg.cfg_core0 + 0x0164)
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#define R_CORE0_T1_MON_SP (scpreg.cfg_core0 + 0x0168)
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#define R_CORE0_T1_MON_PC_LATCH (scpreg.cfg_core0 + 0x0170)
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#define R_CORE0_T1_MON_LR_LATCH (scpreg.cfg_core0 + 0x0174)
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#define R_CORE0_T1_MON_SP_LATCH (scpreg.cfg_core0 + 0x0178)
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#define R_CORE0_TBUF_DATA31_0 (scpreg.cfg_core0 + 0x00e0)
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#define R_CORE0_TBUF_DATA63_32 (scpreg.cfg_core0 + 0x00e4)
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#define R_CORE0_TBUF_DATA95_64 (scpreg.cfg_core0 + 0x00e8)
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#define R_CORE0_TBUF_DATA127_96 (scpreg.cfg_core0 + 0x00ec)
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#define R_CORE0_TBUF1_DATA31_0 (scpreg.cfg_core0 + 0x00f0)
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#define R_CORE0_TBUF1_DATA63_32 (scpreg.cfg_core0 + 0x00f4)
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#define R_CORE0_TBUF1_DATA95_64 (scpreg.cfg_core0 + 0x00f8)
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#define R_CORE0_TBUF1_DATA127_96 (scpreg.cfg_core0 + 0x00fc)
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#define SCP_A_GENERAL_REG0 (scpreg.cfg_core0 + 0x0040)
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/* DRAM reserved address and size */
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#define SCP_A_GENERAL_REG1 (scpreg.cfg_core0 + 0x0044)
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#define DRAM_RESV_ADDR_REG SCP_A_GENERAL_REG1
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#define SCP_A_GENERAL_REG2 (scpreg.cfg_core0 + 0x0048)
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#define DRAM_RESV_SIZE_REG SCP_A_GENERAL_REG2
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/*EXPECTED_FREQ_REG*/
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#define SCP_A_GENERAL_REG3 (scpreg.cfg_core0 + 0x004C)
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#define EXPECTED_FREQ_REG SCP_A_GENERAL_REG3
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/*CURRENT_FREQ_REG*/
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#define SCP_A_GENERAL_REG4 (scpreg.cfg_core0 + 0x0050)
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#define CURRENT_FREQ_REG SCP_A_GENERAL_REG4
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/*SCP_GPR_CM4_A_REBOOT*/
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#define SCP_A_GENERAL_REG5 (scpreg.cfg_core0 + 0x0054)
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#define SCP_GPR_CORE0_REBOOT SCP_A_GENERAL_REG5
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#define CORE_RDY_TO_REBOOT 0x34
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#define CORE_REBOOT_OK 0x1
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#define SCP_A_GENERAL_REG6 (scpreg.cfg_core0 + 0x0058)
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#define SCP_GPR_CORE1_REBOOT SCP_A_GENERAL_REG6
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#define SCP_A_GENERAL_REG7 (scpreg.cfg_core0 + 0x005C)
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/* bus tracker reg */
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#define SCP_BUS_DBG_CON (scpreg.bus_tracker)
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#define SCP_BUS_DBG_AR_TRACK0_L (scpreg.bus_tracker + 0x100)
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#define SCP_BUS_DBG_AR_TRACK1_L (scpreg.bus_tracker + 0x108)
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#define SCP_BUS_DBG_AR_TRACK2_L (scpreg.bus_tracker + 0x110)
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#define SCP_BUS_DBG_AR_TRACK3_L (scpreg.bus_tracker + 0x118)
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#define SCP_BUS_DBG_AR_TRACK4_L (scpreg.bus_tracker + 0x120)
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#define SCP_BUS_DBG_AR_TRACK5_L (scpreg.bus_tracker + 0x128)
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#define SCP_BUS_DBG_AR_TRACK6_L (scpreg.bus_tracker + 0x130)
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#define SCP_BUS_DBG_AR_TRACK7_L (scpreg.bus_tracker + 0x138)
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#define SCP_BUS_DBG_AW_TRACK0_L (scpreg.bus_tracker + 0x300)
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#define SCP_BUS_DBG_AW_TRACK1_L (scpreg.bus_tracker + 0x308)
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#define SCP_BUS_DBG_AW_TRACK2_L (scpreg.bus_tracker + 0x310)
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#define SCP_BUS_DBG_AW_TRACK3_L (scpreg.bus_tracker + 0x318)
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#define SCP_BUS_DBG_AW_TRACK4_L (scpreg.bus_tracker + 0x320)
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#define SCP_BUS_DBG_AW_TRACK5_L (scpreg.bus_tracker + 0x328)
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#define SCP_BUS_DBG_AW_TRACK6_L (scpreg.bus_tracker + 0x330)
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#define SCP_BUS_DBG_AW_TRACK7_L (scpreg.bus_tracker + 0x338)
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/* clk reg*/
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#define SCP_A_SLEEP_DEBUG_REG (scpreg.clkctrl + 0x0028)
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#define SCP_CLK_CTRL_L1_SRAM_PD (scpreg.clkctrl + 0x002C)
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#define SCP_CLK_HIGH_CORE_CG (scpreg.clkctrl + 0x005C)
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#define SCP_CPU0_SRAM_PD (scpreg.clkctrl + 0x0080)
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#define SCP_CPU1_SRAM_PD (scpreg.clkctrl + 0x0084)
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#define SCP_CLK_CTRL_TCM_TAIL_SRAM_PD (scpreg.clkctrl + 0x0094)
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#define CLK_SW_SEL (scpreg.clkctrl + 0x0)
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#define CLK_SW_SEL_O_BIT 8
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#define CLK_SW_SEL_O_MASK 0xf
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#define CLK_SW_SEL_O_ULPOSC_CORE 0x4
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#define CLK_SW_SEL_O_ULPOSC_PERI 0x8
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#define CLK_ENABLE (scpreg.clkctrl + 0x0004)
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#define CLK_SYS_EN_BIT 0
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#define CLK_HIGH_EN_BIT 1
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#define CLK_HIGH_CG_BIT 2
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#define CLK_SYS_IRQ_EN_BIT 16
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#define CLK_HIGH_IRQ_EN_BIT 17
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#define CLK_SAFE_ACK (scpreg.clkctrl + 0x0008)
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#define CLK_SYS_SAFE_ACK_BIT 0
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#define CLK_HIGH_SAFE_ACK_BIT 1
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#define CLK_HIGH_CORE (scpreg.clkctrl + 0x005C)
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#define HIGH_CORE_CG_BIT 1
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#define CLK_ON_CTRL (scpreg.clkctrl + 0x006C)
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#define HIGH_AO_BIT 0
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#define HIGH_CG_AO_BIT 2
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#define HIGH_CORE_AO_BIT 4
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#define HIGH_CORE_DIS_SUB_BIT 5
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#define HIGH_CORE_CG_AO_BIT 6
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#define HIGH_FINAL_VAL_BIT 8
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#define HIGH_FINAL_VAL_MASK 0x1f
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#define R_SEC_CTRL (scpreg.cfg_sec + 0x0000)
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#define B_CORE0_CACHE_DBG_EN (1 << 28)
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#define B_CORE1_CACHE_DBG_EN (1 << 29)
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#define R_CORE0_CACHE_RAM (scpreg.l1cctrl + 0x00000)
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/* INFRA_IRQ (always on register) */
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#define INFRA_IRQ_SET (scpreg.scpsys + 0x0B14)
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#define AP_AWAKE_LOCK (0)
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#define AP_AWAKE_UNLOCK (1)
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#define CONNSYS_AWAKE_LOCK (2)
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#define CONNSYS_AWAKE_UNLOCK (3)
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#define INFRA_IRQ_CLEAR (scpreg.scpsys + 0x0B18)
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#define SCP_SYS_INFRA_MON (scpreg.scpsys + 0x0D50)
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#endif
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