threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
133 lines
5.2 KiB
C
133 lines
5.2 KiB
C
/*
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* Copyright (C) 2016 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See http://www.gnu.org/licenses/gpl-2.0.html for more details.
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*/
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#ifndef __MODEM_DPMAIF_DRV_H__
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#define __MODEM_DPMAIF_DRV_H__
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#include "ccci_config.h"
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#include "dpmaif_reg.h"
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/* == RX part == */
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#ifdef HW_FRG_FEATURE_ENABLE
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unsigned short drv_dpmaif_dl_get_frg_bat_ridx(unsigned char q_num);
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int drv_dpmaif_dl_add_frg_bat_cnt(unsigned char q_num,
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unsigned short frg_entry_cnt);
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#endif
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unsigned short drv_dpmaif_dl_get_bat_ridx(unsigned char q_num);
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int drv_dpmaif_dl_add_bat_cnt(unsigned char q_num,
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unsigned short bat_entry_cnt);
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int drv_dpmaif_dl_add_pit_remain_cnt(unsigned char q_num,
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unsigned short pit_remain_cnt);
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unsigned int drv_dpmaif_dl_get_wridx(unsigned char q_num);
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void drv_dpmaif_mask_dl_interrupt(unsigned char q_num);
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void drv_dpmaif_unmask_dl_interrupt(unsigned char q_num);
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int drv_dpmaif_dl_all_queue_en(bool enable);
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unsigned int drv_dpmaif_dl_idle_check(void);
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/* == TX part == */
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void drv_dpmaif_mask_ul_que_interrupt(unsigned char q_num);
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void drv_dpmaif_unmask_ul_interrupt(unsigned char q_num);
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unsigned int drv_dpmaif_ul_get_ridx(unsigned char q_num);
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unsigned int drv_dpmaif_ul_get_rwidx(unsigned char q_num);
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unsigned int drv_dpmaif_ul_get_hw_widx_01(void);
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int drv_dpmaif_ul_add_wcnt(unsigned char q_num, unsigned short drb_wcnt);
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/* isr part */
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#define drv_dpmaif_get_dl_isr_event() \
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DPMA_READ_PD_MISC(DPMAIF_PD_AP_DL_L2TISAR0)
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#define drv_dpmaif_get_ul_isr_event() \
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DPMA_READ_PD_MISC(DPMAIF_PD_AP_UL_L2TISAR0)
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#define drv_dpmaif_get_dl_interrupt_mask() \
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DPMA_READ_PD_MISC(DPMAIF_PD_AP_DL_L2TIMR0)
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/* use ao domain:
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* (DPMA_READ_AO_DL(DPMAIF_AO_DL_RDY_CHK_THRES)&DPMAIF_AO_DL_ISR_MSK)
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*/
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#ifdef MT6297
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#define drv_dpmaif_ul_get_ul_interrupt_mask() \
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DPMA_READ_AO_UL(DPMAIF_PD_AP_UL_L2TIMR0)
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#else
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#define drv_dpmaif_ul_get_ul_interrupt_mask() \
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DPMA_READ_PD_MISC(DPMAIF_PD_AP_UL_L2TIMR0)
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#endif
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void drv_dpmaif_clear_ip_busy(void);
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/* == state part == */
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/*void drv_dpmaif_set_dl_interrupt_mask(unsigned int mask);*/
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int drv_dpmaif_intr_hw_init(void);
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/* init: rx init */
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int drv_dpmaif_dl_bat_init_done(unsigned char q_num, bool frg_en);
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void drv_dpmaif_dl_pit_init_done(unsigned char q_num);
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void drv_dpmaif_dl_set_bat_base_addr(unsigned char q_num,
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dma_addr_t base_addr);
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void drv_dpmaif_dl_set_bat_size(unsigned char q_num, unsigned int size);
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void drv_dpmaif_dl_bat_en(unsigned char q_num, bool enable);
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void drv_dpmaif_dl_set_pit_base_addr(unsigned char q_num,
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dma_addr_t base_addr);
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void drv_dpmaif_dl_set_pit_size(unsigned char q_num, unsigned int size);
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void drv_dpmaif_dl_pit_en(unsigned char q_num, bool enable);
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void drv_dpmaif_dl_set_bid_maxcnt(unsigned char q_num, unsigned int cnt);
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void drv_dpmaif_dl_set_remain_minsz(unsigned char q_num, unsigned int sz);
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#ifdef _HW_REORDER_SW_WORKAROUND_
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void drv_dpmaif_dl_set_apit_idx(unsigned char q_num, unsigned int idx);
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int drv_dpmaif_dl_add_apit_num(unsigned short ap_entry_cnt);
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#endif
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void drv_dpmaif_dl_set_mtu(unsigned int mtu_sz);
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void drv_dpmaif_dl_set_pit_chknum(unsigned char q_num, unsigned int number);
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void drv_dpmaif_dl_set_bat_bufsz(unsigned char q_num, unsigned int buf_sz);
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void drv_dpmaif_dl_set_bat_rsv_len(unsigned char q_num, unsigned int length);
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void drv_dpmaif_dl_set_pkt_align(unsigned char q_num, bool enable,
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unsigned int mode);
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void drv_dpmaif_dl_set_bat_chk_thres(unsigned char q_num, unsigned int size);
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#ifdef HW_FRG_FEATURE_ENABLE
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void drv_dpmaif_dl_set_ao_frag_check_thres(unsigned char q_num,
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unsigned int size);
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void drv_dpmaif_dl_set_ao_frg_bat_feature(unsigned char q_num, bool enable);
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void drv_dpmaif_dl_set_ao_frg_bat_bufsz(unsigned char q_num,
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unsigned int buf_sz);
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int drv_dpmaif_dl_all_frg_queue_en(bool enable);
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#endif
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#ifdef HW_CHECK_SUM_ENABLE
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void drv_dpmaif_dl_set_ao_chksum_en(unsigned char q_num, bool enable);
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#endif
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/* init: tx init */
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void drv_dpmaif_init_ul_intr(void);
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void drv_dpmaif_ul_update_drb_size(unsigned char q_num, unsigned int size);
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void drv_dpmaif_ul_update_drb_base_addr(unsigned char q_num,
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unsigned int lb_addr, unsigned int hb_addr);
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void drv_dpmaif_ul_rdy_en(unsigned char q_num, bool ready);
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void drv_dpmaif_ul_arb_en(unsigned char q_num, bool enable);
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void drv_dpmaif_ul_all_queue_en(bool enable);
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unsigned int drv_dpmaif_ul_idle_check(void);
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/* suspend resume */
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bool drv_dpmaif_check_power_down(void);
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int drv_dpmaif_dl_restore(unsigned int mask);
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#ifdef _E1_SB_SW_WORKAROUND_
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unsigned int drv_dpmaif_dl_get_pit_ridx(unsigned char q_num);
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unsigned int drv_dpmaif_dl_get_bat_wridx(unsigned char q_num);
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void drv_dpmaif_unmask_dl_full_intr(unsigned char q_num);
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void dpmaif_mask_pitcnt_len_error_intr(unsigned char q_num);
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void dpmaif_mask_batcnt_len_error_intr(unsigned char q_num);
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#endif
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#ifdef MT6297
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void drv_dpmaif_dl_set_performance(void);
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void drv_dpmaif_dl_set_wdma(void);
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void drv_dpmaif_dl_set_chk_rbnum(unsigned char q_num, unsigned int cnt);
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void drv_dpmaif_common_hw_init(void);
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void drv_dpmaif_md_hw_bus_remap(void);
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#endif
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#endif
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