threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
49 lines
1.8 KiB
C
49 lines
1.8 KiB
C
/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "i915_drv.h"
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#include "i915_gem_object.h"
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/**
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* Mark up the object's coherency levels for a given cache_level
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* @obj: #drm_i915_gem_object
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* @cache_level: cache level
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*/
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void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj,
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unsigned int cache_level)
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{
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obj->cache_level = cache_level;
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if (cache_level != I915_CACHE_NONE)
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obj->cache_coherent = (I915_BO_CACHE_COHERENT_FOR_READ |
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I915_BO_CACHE_COHERENT_FOR_WRITE);
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else if (HAS_LLC(to_i915(obj->base.dev)))
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obj->cache_coherent = I915_BO_CACHE_COHERENT_FOR_READ;
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else
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obj->cache_coherent = 0;
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obj->cache_dirty =
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!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE);
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}
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