threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
92 lines
2.3 KiB
C
92 lines
2.3 KiB
C
/*
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* Clocks for ux500 platforms
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*
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* Copyright (C) 2012 ST-Ericsson SA
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* Author: Ulf Hansson <ulf.hansson@linaro.org>
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#ifndef __UX500_CLK_H
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#define __UX500_CLK_H
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#include <linux/device.h>
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#include <linux/types.h>
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struct clk;
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struct clk *clk_reg_prcc_pclk(const char *name,
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const char *parent_name,
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resource_size_t phy_base,
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u32 cg_sel,
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unsigned long flags);
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struct clk *clk_reg_prcc_kclk(const char *name,
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const char *parent_name,
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resource_size_t phy_base,
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u32 cg_sel,
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unsigned long flags);
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struct clk *clk_reg_prcmu_scalable(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long rate,
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unsigned long flags);
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struct clk *clk_reg_prcmu_gate(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long flags);
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struct clk *clk_reg_prcmu_scalable_rate(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long rate,
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unsigned long flags);
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struct clk *clk_reg_prcmu_rate(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long flags);
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struct clk *clk_reg_prcmu_opp_gate(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long flags);
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struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
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const char *parent_name,
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u8 cg_sel,
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unsigned long rate,
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unsigned long flags);
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struct clk *clk_reg_sysctrl_gate(struct device *dev,
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const char *name,
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const char *parent_name,
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u16 reg_sel,
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u8 reg_mask,
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u8 reg_bits,
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unsigned long enable_delay_us,
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unsigned long flags);
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struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
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const char *name,
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const char *parent_name,
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u16 reg_sel,
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u8 reg_mask,
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u8 reg_bits,
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unsigned long rate,
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unsigned long enable_delay_us,
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unsigned long flags);
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struct clk *clk_reg_sysctrl_set_parent(struct device *dev,
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const char *name,
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const char **parent_names,
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u8 num_parents,
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u16 *reg_sel,
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u8 *reg_mask,
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u8 *reg_bits,
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unsigned long flags);
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#endif /* __UX500_CLK_H */
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