threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
86 lines
2.5 KiB
C
86 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_MICROCODE_INTEL_H
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#define _ASM_X86_MICROCODE_INTEL_H
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#include <asm/microcode.h>
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struct microcode_header_intel {
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unsigned int hdrver;
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unsigned int rev;
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unsigned int date;
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unsigned int sig;
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unsigned int cksum;
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unsigned int ldrver;
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unsigned int pf;
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unsigned int datasize;
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unsigned int totalsize;
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unsigned int reserved[3];
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};
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struct microcode_intel {
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struct microcode_header_intel hdr;
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unsigned int bits[0];
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};
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/* microcode format is extended from prescott processors */
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struct extended_signature {
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unsigned int sig;
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unsigned int pf;
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unsigned int cksum;
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};
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struct extended_sigtable {
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unsigned int count;
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unsigned int cksum;
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unsigned int reserved[3];
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struct extended_signature sigs[0];
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};
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#define DEFAULT_UCODE_DATASIZE (2000)
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#define MC_HEADER_SIZE (sizeof(struct microcode_header_intel))
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#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)
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#define EXT_HEADER_SIZE (sizeof(struct extended_sigtable))
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#define EXT_SIGNATURE_SIZE (sizeof(struct extended_signature))
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#define get_totalsize(mc) \
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(((struct microcode_intel *)mc)->hdr.datasize ? \
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((struct microcode_intel *)mc)->hdr.totalsize : \
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DEFAULT_UCODE_TOTALSIZE)
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#define get_datasize(mc) \
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(((struct microcode_intel *)mc)->hdr.datasize ? \
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((struct microcode_intel *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE)
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#define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE)
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static inline u32 intel_get_microcode_revision(void)
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{
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u32 rev, dummy;
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native_wrmsrl(MSR_IA32_UCODE_REV, 0);
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/* As documented in the SDM: Do a CPUID 1 here */
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native_cpuid_eax(1);
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/* get the current revision from MSR 0x8B */
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native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev);
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return rev;
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}
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#ifdef CONFIG_MICROCODE_INTEL
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extern void __init load_ucode_intel_bsp(void);
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extern void load_ucode_intel_ap(void);
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extern void show_ucode_info_early(void);
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extern int __init save_microcode_in_initrd_intel(void);
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void reload_ucode_intel(void);
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#else
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static inline __init void load_ucode_intel_bsp(void) {}
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static inline void load_ucode_intel_ap(void) {}
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static inline void show_ucode_info_early(void) {}
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static inline int __init save_microcode_in_initrd_intel(void) { return -EINVAL; }
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static inline void reload_ucode_intel(void) {}
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#endif
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#endif /* _ASM_X86_MICROCODE_INTEL_H */
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