threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
90 lines
1.7 KiB
ArmAsm
90 lines
1.7 KiB
ArmAsm
/*
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* linux/arch/unicore32/mm/tlb-ucv2.S
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/page.h>
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#include <asm/tlbflush.h>
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#include "proc-macros.S"
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/*
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* __cpu_flush_user_tlb_range(start, end, vma)
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*
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* Invalidate a range of TLB entries in the specified address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - vma - vma_struct describing address range
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*/
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ENTRY(__cpu_flush_user_tlb_range)
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#ifndef CONFIG_CPU_TLB_SINGLE_ENTRY_DISABLE
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mov r0, r0 >> #PAGE_SHIFT @ align address
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mov r0, r0 << #PAGE_SHIFT
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vma_vm_flags r2, r2 @ get vma->vm_flags
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1:
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movc p0.c6, r0, #3
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nop8
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cand.a r2, #VM_EXEC @ Executable area ?
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beq 2f
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movc p0.c6, r0, #5
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nop8
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2:
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add r0, r0, #PAGE_SZ
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csub.a r0, r1
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beb 1b
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#else
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movc p0.c6, r0, #2
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nop8
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cand.a r2, #VM_EXEC @ Executable area ?
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beq 2f
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movc p0.c6, r0, #4
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nop8
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2:
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#endif
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mov pc, lr
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/*
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* __cpu_flush_kern_tlb_range(start,end)
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*
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* Invalidate a range of kernel TLB entries
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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*/
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ENTRY(__cpu_flush_kern_tlb_range)
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#ifndef CONFIG_CPU_TLB_SINGLE_ENTRY_DISABLE
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mov r0, r0 >> #PAGE_SHIFT @ align address
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mov r0, r0 << #PAGE_SHIFT
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1:
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movc p0.c6, r0, #3
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nop8
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movc p0.c6, r0, #5
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nop8
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add r0, r0, #PAGE_SZ
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csub.a r0, r1
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beb 1b
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#else
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movc p0.c6, r0, #2
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nop8
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movc p0.c6, r0, #4
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nop8
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#endif
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mov pc, lr
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