threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
88 lines
2.1 KiB
C
88 lines
2.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 by Ralf Baechle
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*/
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#ifndef __ASM_PREFETCH_H
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#define __ASM_PREFETCH_H
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/*
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* R5000 and RM5200 implements pref and prefx instructions but they're nops, so
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* rather than wasting time we pretend these processors don't support
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* prefetching at all.
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*
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* R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained,
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* StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore.
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*
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* Hell (and the book on my shelf I can't open ...) know what the R8000 does.
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*
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* RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements
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* Pref_PrepareForStore also.
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*
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* RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; it's
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* Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
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* current versions due to erratum G105.
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*
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* VR5500 (including VR5701 and VR7701) only implement load prefetch.
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*
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* Finally MIPS32 and MIPS64 implement all of the following hints.
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*/
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#define Pref_Load 0
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#define Pref_Store 1
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/* 2 and 3 are reserved */
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#define Pref_LoadStreamed 4
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#define Pref_StoreStreamed 5
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#define Pref_LoadRetained 6
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#define Pref_StoreRetained 7
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/* 8 ... 24 are reserved */
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#define Pref_WriteBackInvalidate 25
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#define Pref_PrepareForStore 30
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#ifdef __ASSEMBLY__
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.macro __pref hint addr
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#ifdef CONFIG_CPU_HAS_PREFETCH
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pref \hint, \addr
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#endif
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.endm
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.macro pref_load addr
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__pref Pref_Load, \addr
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.endm
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.macro pref_store addr
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__pref Pref_Store, \addr
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.endm
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.macro pref_load_streamed addr
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__pref Pref_LoadStreamed, \addr
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.endm
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.macro pref_store_streamed addr
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__pref Pref_StoreStreamed, \addr
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.endm
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.macro pref_load_retained addr
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__pref Pref_LoadRetained, \addr
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.endm
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.macro pref_store_retained addr
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__pref Pref_StoreRetained, \addr
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.endm
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.macro pref_wback_inv addr
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__pref Pref_WriteBackInvalidate, \addr
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.endm
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.macro pref_prepare_for_store addr
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__pref Pref_PrepareForStore, \addr
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.endm
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#endif
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#endif /* __ASM_PREFETCH_H */
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