threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
99 lines
2.8 KiB
ArmAsm
99 lines
2.8 KiB
ArmAsm
/* cache.S: cache management routines
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/spr-regs.h>
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#include <asm/cache.h>
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.text
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.p2align 4
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###############################################################################
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#
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# Write back a range of dcache
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# - void frv_dcache_writeback(unsigned long start [GR8], unsigned long size [GR9])
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#
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###############################################################################
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.globl frv_dcache_writeback
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.type frv_dcache_writeback,@function
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frv_dcache_writeback:
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andi gr8,~(L1_CACHE_BYTES-1),gr8
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2: dcf @(gr8,gr0)
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addi gr8,#L1_CACHE_BYTES,gr8
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cmp gr9,gr8,icc0
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bhi icc0,#2,2b
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membar
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bralr
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.size frv_dcache_writeback, .-frv_dcache_writeback
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##############################################################################
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#
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# Invalidate a range of dcache and icache
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# - void frv_cache_invalidate(unsigned long start [GR8], unsigned long end [GR9]);
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#
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###############################################################################
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.globl frv_cache_invalidate
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.type frv_cache_invalidate,@function
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frv_cache_invalidate:
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andi gr8,~(L1_CACHE_BYTES-1),gr8
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2: dci @(gr8,gr0)
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ici @(gr8,gr0)
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addi gr8,#L1_CACHE_BYTES,gr8
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cmp gr9,gr8,icc0
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bhi icc0,#2,2b
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membar
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bralr
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.size frv_cache_invalidate, .-frv_cache_invalidate
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##############################################################################
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#
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# Invalidate a range of icache
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# - void frv_icache_invalidate(unsigned long start [GR8], unsigned long end [GR9]);
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#
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###############################################################################
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.globl frv_icache_invalidate
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.type frv_icache_invalidate,@function
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frv_icache_invalidate:
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andi gr8,~(L1_CACHE_BYTES-1),gr8
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2: ici @(gr8,gr0)
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addi gr8,#L1_CACHE_BYTES,gr8
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cmp gr9,gr8,icc0
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bhi icc0,#2,2b
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membar
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bralr
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.size frv_icache_invalidate, .-frv_icache_invalidate
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###############################################################################
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#
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# Write back and invalidate a range of dcache and icache
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# - void frv_cache_wback_inv(unsigned long start [GR8], unsigned long end [GR9])
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#
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###############################################################################
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.globl frv_cache_wback_inv
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.type frv_cache_wback_inv,@function
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frv_cache_wback_inv:
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andi gr8,~(L1_CACHE_BYTES-1),gr8
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2: dcf @(gr8,gr0)
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ici @(gr8,gr0)
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addi gr8,#L1_CACHE_BYTES,gr8
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cmp gr9,gr8,icc0
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bhi icc0,#2,2b
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membar
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bralr
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.size frv_cache_wback_inv, .-frv_cache_wback_inv
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