threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
72 lines
2.3 KiB
ArmAsm
72 lines
2.3 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This table is used by some tools to extract hardware parameters.
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* The table should be included in the kernel and the decompressor.
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* Don't forget to update the tools if you change this table.
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*
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* Copyright (C) 2001-2007 Axis Communications AB
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*
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* Authors: Mikael Starvik <starvik@axis.com>
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*/
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#include <hwregs/asm/reg_map_asm.h>
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#include <hwregs/asm/bif_core_defs_asm.h>
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#include <hwregs/asm/gio_defs_asm.h>
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.ascii "HW_PARAM_MAGIC" ; Magic number
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.dword 0xc0004000 ; Kernel start address
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; Debug port
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#ifdef CONFIG_ETRAX_DEBUG_PORT0
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.dword 0
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#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
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.dword 1
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#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
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.dword 2
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#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
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.dword 3
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#else
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.dword 4 ; No debug
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#endif
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; Register values
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.dword REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg)
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.dword CONFIG_ETRAX_MEM_GRP1_CONFIG
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.dword REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg)
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.dword CONFIG_ETRAX_MEM_GRP2_CONFIG
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.dword REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg)
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.dword CONFIG_ETRAX_MEM_GRP3_CONFIG
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.dword REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg)
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.dword CONFIG_ETRAX_MEM_GRP4_CONFIG
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.dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp0)
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.dword CONFIG_ETRAX_SDRAM_GRP0_CONFIG
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.dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cfg_grp1)
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.dword CONFIG_ETRAX_SDRAM_GRP1_CONFIG
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.dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_timing)
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.dword CONFIG_ETRAX_SDRAM_TIMING
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.dword REG_ADDR(bif_core, regi_bif_core, rw_sdram_cmd)
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.dword CONFIG_ETRAX_SDRAM_COMMAND
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.dword REG_ADDR(gio, regi_gio, rw_pa_dout)
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.dword CONFIG_ETRAX_DEF_GIO_PA_OUT
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.dword REG_ADDR(gio, regi_gio, rw_pa_oe)
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.dword CONFIG_ETRAX_DEF_GIO_PA_OE
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.dword REG_ADDR(gio, regi_gio, rw_pb_dout)
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.dword CONFIG_ETRAX_DEF_GIO_PB_OUT
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.dword REG_ADDR(gio, regi_gio, rw_pb_oe)
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.dword CONFIG_ETRAX_DEF_GIO_PB_OE
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.dword REG_ADDR(gio, regi_gio, rw_pc_dout)
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.dword CONFIG_ETRAX_DEF_GIO_PC_OUT
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.dword REG_ADDR(gio, regi_gio, rw_pc_oe)
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.dword CONFIG_ETRAX_DEF_GIO_PC_OE
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.dword REG_ADDR(gio, regi_gio, rw_pd_dout)
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.dword CONFIG_ETRAX_DEF_GIO_PD_OUT
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.dword REG_ADDR(gio, regi_gio, rw_pd_oe)
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.dword CONFIG_ETRAX_DEF_GIO_PD_OE
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.dword REG_ADDR(gio, regi_gio, rw_pe_dout)
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.dword CONFIG_ETRAX_DEF_GIO_PE_OUT
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.dword REG_ADDR(gio, regi_gio, rw_pe_oe)
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.dword CONFIG_ETRAX_DEF_GIO_PE_OE
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.dword 0 ; No more register values
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