threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
45 lines
1.5 KiB
C
45 lines
1.5 KiB
C
/*
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* Set up the interrupt priorities
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*
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* Copyright 2005-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <asm/blackfin.h>
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void __init program_IAR(void)
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{
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/* Program the IAR0 Register with the configured priority */
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bfin_write_SIC_IAR0(((CONFIG_PLLWAKE_ERROR - 7) << PLLWAKE_ERROR_POS) |
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((CONFIG_DMA_ERROR - 7) << DMA_ERROR_POS) |
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((CONFIG_PPI_ERROR - 7) << PPI_ERROR_POS) |
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((CONFIG_SPORT0_ERROR - 7) << SPORT0_ERROR_POS) |
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((CONFIG_SPI_ERROR - 7) << SPI_ERROR_POS) |
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((CONFIG_SPORT1_ERROR - 7) << SPORT1_ERROR_POS) |
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((CONFIG_UART_ERROR - 7) << UART_ERROR_POS) |
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((CONFIG_RTC_ERROR - 7) << RTC_ERROR_POS));
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bfin_write_SIC_IAR1(((CONFIG_DMA0_PPI - 7) << DMA0_PPI_POS) |
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((CONFIG_DMA1_SPORT0RX - 7) << DMA1_SPORT0RX_POS) |
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((CONFIG_DMA2_SPORT0TX - 7) << DMA2_SPORT0TX_POS) |
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((CONFIG_DMA3_SPORT1RX - 7) << DMA3_SPORT1RX_POS) |
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((CONFIG_DMA4_SPORT1TX - 7) << DMA4_SPORT1TX_POS) |
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((CONFIG_DMA5_SPI - 7) << DMA5_SPI_POS) |
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((CONFIG_DMA6_UARTRX - 7) << DMA6_UARTRX_POS) |
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((CONFIG_DMA7_UARTTX - 7) << DMA7_UARTTX_POS));
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bfin_write_SIC_IAR2(((CONFIG_TIMER0 - 7) << TIMER0_POS) |
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((CONFIG_TIMER1 - 7) << TIMER1_POS) |
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((CONFIG_TIMER2 - 7) << TIMER2_POS) |
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((CONFIG_PFA - 7) << PFA_POS) |
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((CONFIG_PFB - 7) << PFB_POS) |
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((CONFIG_MEMDMA0 - 7) << MEMDMA0_POS) |
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((CONFIG_MEMDMA1 - 7) << MEMDMA1_POS) |
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((CONFIG_WDTIMER - 7) << WDTIMER_POS));
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SSYNC();
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}
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