threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
39 lines
1017 B
C
39 lines
1017 B
C
/* arch/arm/plat-s3c64xx/include/plat/regs-clock.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX clock register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PLAT_REGS_CLOCK_H
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#define __PLAT_REGS_CLOCK_H __FILE__
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/*
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* FIXME: Remove remaining definitions
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*/
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#define S3C_CLKREG(x) (S3C_VA_SYS + (x))
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#define S3C_PCLK_GATE S3C_CLKREG(0x34)
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#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C)
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#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120)
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/* PCLK GATE Registers */
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#define S3C_CLKCON_PCLK_UART3 (1<<4)
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#define S3C_CLKCON_PCLK_UART2 (1<<3)
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#define S3C_CLKCON_PCLK_UART1 (1<<2)
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#define S3C_CLKCON_PCLK_UART0 (1<<1)
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/* MEM_SYS_CFG */
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#define MEM_SYS_CFG_INDEP_CF 0x4000
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#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30
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#endif /* _PLAT_REGS_CLOCK_H */
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