threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
60 lines
1.4 KiB
C
60 lines
1.4 KiB
C
/*
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* OMAP2-specific DPLL control functions
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*
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* Copyright (C) 2011 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include "clock.h"
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#include "cm2xxx.h"
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#include "cm-regbits-24xx.h"
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/* Private functions */
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/**
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* _allow_idle - enable DPLL autoidle bits
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* @clk: struct clk * of the DPLL to operate on
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*
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* Enable DPLL automatic idle control. The DPLL will enter low-power
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* stop when its downstream clocks are gated. No return value.
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* REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
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* instead. Add some mechanism to optionally enter this mode.
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*/
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static void _allow_idle(struct clk_hw_omap *clk)
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{
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if (!clk || !clk->dpll_data)
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return;
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omap2xxx_cm_set_dpll_auto_low_power_stop();
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}
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/**
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* _deny_idle - prevent DPLL from automatically idling
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* @clk: struct clk * of the DPLL to operate on
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*
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* Disable DPLL automatic idle control. No return value.
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*/
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static void _deny_idle(struct clk_hw_omap *clk)
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{
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if (!clk || !clk->dpll_data)
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return;
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omap2xxx_cm_set_dpll_disable_autoidle();
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}
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/* Public data */
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const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll = {
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.allow_idle = _allow_idle,
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.deny_idle = _deny_idle,
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};
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