threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
39 lines
1.4 KiB
Plaintext
39 lines
1.4 KiB
Plaintext
MediaTek PWM controller
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Required properties:
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- compatible: should be "mediatek,<name>-pwm":
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- "mediatek,mt2712-pwm": found on mt2712 SoC.
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- "mediatek,mt7622-pwm": found on mt7622 SoC.
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- "mediatek,mt7623-pwm": found on mt7623 SoC.
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- reg: physical base address and length of the controller's registers.
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- #pwm-cells: must be 2. See pwm.txt in this directory for a description of
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the cell format.
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- clocks: phandle and clock specifier of the PWM reference clock.
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- clock-names: must contain the following:
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- "top": the top clock generator
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- "main": clock used by the PWM core
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- "pwm1-8": the eight per PWM clocks for mt2712
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- "pwm1-6": the six per PWM clocks for mt7622
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- "pwm1-5": the five per PWM clocks for mt7623
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- pinctrl-names: Must contain a "default" entry.
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- pinctrl-0: One property must exist for each entry in pinctrl-names.
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See pinctrl/pinctrl-bindings.txt for details of the property values.
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Example:
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pwm0: pwm@11006000 {
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compatible = "mediatek,mt7623-pwm";
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reg = <0 0x11006000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&topckgen CLK_TOP_PWM_SEL>,
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<&pericfg CLK_PERI_PWM>,
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<&pericfg CLK_PERI_PWM1>,
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<&pericfg CLK_PERI_PWM2>,
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<&pericfg CLK_PERI_PWM3>,
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<&pericfg CLK_PERI_PWM4>,
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<&pericfg CLK_PERI_PWM5>;
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clock-names = "top", "main", "pwm1", "pwm2",
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"pwm3", "pwm4", "pwm5";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pins>;
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};
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