threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
107 lines
2.2 KiB
Plaintext
107 lines
2.2 KiB
Plaintext
Texas Instruments VPIF
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----------------------
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The TI Video Port InterFace (VPIF) is the primary component for video
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capture and display on the DA850/AM18x family of TI DaVinci/Sitara
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SoCs.
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TI Document reference: SPRUH82C, Chapter 35
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http://www.ti.com/lit/pdf/spruh82
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Required properties:
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- compatible: must be "ti,da850-vpif"
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- reg: physical base address and length of the registers set for the device;
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- interrupts: should contain IRQ line for the VPIF
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Video Capture:
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VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a
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single 16-bit channel. It should contain one or two port child nodes
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with child 'endpoint' node. If there are two ports then port@0 must
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describe the input and port@1 output channels. Please refer to the
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bindings defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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Example using 2 8-bit input channels, one of which is connected to an
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I2C-connected TVP5147 decoder:
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vpif: vpif@217000 {
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compatible = "ti,da850-vpif";
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reg = <0x217000 0x1000>;
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interrupts = <92>;
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port@0 {
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vpif_input_ch0: endpoint@0 {
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reg = <0>;
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bus-width = <8>;
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remote-endpoint = <&composite_in>;
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};
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vpif_input_ch1: endpoint@1 {
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reg = <1>;
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bus-width = <8>;
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data-shift = <8>;
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};
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};
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port@1 {
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vpif_output_ch0: endpoint {
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bus-width = <8>;
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remote-endpoint = <&composite_out>;
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};
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};
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};
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[ ... ]
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&i2c0 {
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tvp5147@5d {
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compatible = "ti,tvp5147";
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reg = <0x5d>;
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port {
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composite_in: endpoint {
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hsync-active = <1>;
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vsync-active = <1>;
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pclk-sample = <0>;
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/* VPIF channel 0 (lower 8-bits) */
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remote-endpoint = <&vpif_input_ch0>;
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bus-width = <8>;
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};
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};
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};
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adv7343@2a {
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compatible = "adi,adv7343";
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reg = <0x2a>;
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port {
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composite_out: endpoint {
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adi,dac-enable = <1 1 1>;
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adi,sd-dac-enable = <1>;
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remote-endpoint = <&vpif_output_ch0>;
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bus-width = <8>;
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};
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};
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};
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};
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Alternatively, an example when the bus is configured as a single
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16-bit input (e.g. for raw-capture mode):
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vpif: vpif@217000 {
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compatible = "ti,da850-vpif";
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reg = <0x217000 0x1000>;
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interrupts = <92>;
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port {
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vpif_ch0: endpoint {
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bus-width = <16>;
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};
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};
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};
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