threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
89 lines
3.2 KiB
Plaintext
89 lines
3.2 KiB
Plaintext
STMicroelectronics STi c8sectpfe binding
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============================================
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This document describes the c8sectpfe device bindings that is used to get transport
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stream data into the SoC on the TS pins, and into DDR for further processing.
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It is typically used in conjunction with one or more demodulator and tuner devices
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which converts from the RF to digital domain. Demodulators and tuners are usually
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located on an external DVB frontend card connected to SoC TS input pins.
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Currently 7 TS input (tsin) channels are supported on the stih407 family SoC.
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Required properties (controller (parent) node):
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- compatible : Should be "stih407-c8sectpfe"
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- reg : Address and length of register sets for each device in
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"reg-names"
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- reg-names : The names of the register addresses corresponding to the
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registers filled in "reg":
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- c8sectpfe: c8sectpfe registers
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- c8sectpfe-ram: c8sectpfe internal sram
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- clocks : phandle list of c8sectpfe clocks
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- clock-names : should be "c8sectpfe"
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See: Documentation/devicetree/bindings/clock/clock-bindings.txt
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- pinctrl-names : a pinctrl state named tsin%d-serial or tsin%d-parallel (where %d is tsin-num)
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must be defined for each tsin child node.
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- pinctrl-0 : phandle referencing pin configuration for this tsin configuration
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See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
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Required properties (tsin (child) node):
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- tsin-num : tsin id of the InputBlock (must be between 0 to 6)
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- i2c-bus : phandle to the I2C bus DT node which the demodulators & tuners on this tsin channel are connected.
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- reset-gpios : reset gpio for this tsin channel.
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Optional properties (tsin (child) node):
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- invert-ts-clk : Bool property to control sense of ts input clock (data stored on falling edge of clk).
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- serial-not-parallel : Bool property to configure input bus width (serial on ts_data<7>).
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- async-not-sync : Bool property to control if data is received in asynchronous mode
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(all bits/bytes with ts_valid or ts_packet asserted are valid).
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- dvb-card : Describes the NIM card connected to this tsin channel.
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Example:
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/* stih410 SoC b2120 + b2004a + stv0367-pll(NIMB) + stv0367-tda18212 (NIMA) DT example) */
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c8sectpfe@08a20000 {
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compatible = "st,stih407-c8sectpfe";
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reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>;
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reg-names = "stfe", "stfe-ram";
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interrupts = <GIC_SPI 34 IRQ_TYPE_NONE>, <GIC_SPI 35 IRQ_TYPE_NONE>;
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interrupt-names = "stfe-error-irq", "stfe-idle-irq";
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pinctrl-0 = <&pinctrl_tsin0_serial>;
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pinctrl-1 = <&pinctrl_tsin0_parallel>;
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pinctrl-2 = <&pinctrl_tsin3_serial>;
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pinctrl-3 = <&pinctrl_tsin4_serial_alt3>;
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pinctrl-4 = <&pinctrl_tsin5_serial_alt1>;
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pinctrl-names = "tsin0-serial",
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"tsin0-parallel",
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"tsin3-serial",
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"tsin4-serial",
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"tsin5-serial";
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clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>;
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clock-names = "c8sectpfe";
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/* tsin0 is TSA on NIMA */
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tsin0: port@0 {
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tsin-num = <0>;
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serial-not-parallel;
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i2c-bus = <&ssc2>;
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reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>;
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dvb-card = <STV0367_TDA18212_NIMA_1>;
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};
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tsin3: port@3 {
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tsin-num = <3>;
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serial-not-parallel;
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i2c-bus = <&ssc3>;
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reset-gpios = <&pio15 7 GPIO_ACTIVE_HIGH>;
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dvb-card = <STV0367_TDA18212_NIMB_1>;
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};
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};
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