threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
37 lines
1.1 KiB
Plaintext
37 lines
1.1 KiB
Plaintext
* ARM Nested Vector Interrupt Controller (NVIC)
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The NVIC provides an interrupt controller that is tightly coupled to
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Cortex-M based processor cores. The NVIC implemented on different SoCs
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vary in the number of interrupts and priority bits per interrupt.
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Main node required properties:
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- compatible : should be one of:
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"arm,v6m-nvic"
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"arm,v7m-nvic"
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"arm,v8m-nvic"
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The type shall be a <u32> and the value shall be 2.
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The 1st cell contains the interrupt number for the interrupt type.
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The 2nd cell is the priority of the interrupt.
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- reg : Specifies base physical address(s) and size of the NVIC registers.
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This is at a fixed address (0xe000e100) and size (0xc00).
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- arm,num-irq-priority-bits: The number of priority bits implemented by the
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given SoC
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Example:
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intc: interrupt-controller@e000e100 {
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compatible = "arm,v7m-nvic";
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#interrupt-cells = <2>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0xe000e100 0xc00>;
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arm,num-irq-priority-bits = <4>;
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};
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