threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
24 lines
708 B
Plaintext
24 lines
708 B
Plaintext
* Sigma Designs Tango4 Clock Generator
|
|
|
|
The Tango4 clock generator outputs cpu_clk and sys_clk (the latter is used
|
|
for RAM and various peripheral devices). The clock binding described here
|
|
is applicable to all Tango4 SoCs.
|
|
|
|
Required Properties:
|
|
|
|
- compatible: should be "sigma,tango4-clkgen".
|
|
- reg: physical base address of the device and length of memory mapped region.
|
|
- clocks: phandle of the input clock (crystal oscillator).
|
|
- clock-output-names: should be "cpuclk" and "sysclk".
|
|
- #clock-cells: should be set to 1.
|
|
|
|
Example:
|
|
|
|
clkgen: clkgen@10000 {
|
|
compatible = "sigma,tango4-clkgen";
|
|
reg = <0x10000 0x40>;
|
|
clocks = <&xtal>;
|
|
clock-output-names = "cpuclk", "sysclk";
|
|
#clock-cells = <1>;
|
|
};
|