threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
45 lines
1.7 KiB
Plaintext
45 lines
1.7 KiB
Plaintext
* Calxeda AHCI SATA Controller
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SATA nodes are defined to describe on-chip Serial ATA controllers.
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The Calxeda SATA controller mostly conforms to the AHCI interface
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with some special extensions to add functionality.
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Each SATA controller should have its own node.
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Required properties:
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- compatible : compatible list, contains "calxeda,hb-ahci"
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- interrupts : <interrupt mapping for SATA IRQ>
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- reg : <registers mapping>
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Optional properties:
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- dma-coherent : Present if dma operations are coherent
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- calxeda,port-phys : phandle-combophy and lane assignment, which maps each
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SATA port to a combophy and a lane within that
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combophy
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- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
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which indicates that the driver supports SGPIO
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indicator lights using the indicated GPIOs
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- calxeda,led-order : a u32 array that map port numbers to offsets within the
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SGPIO bitstream.
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- calxeda,tx-atten : a u32 array that contains TX attenuation override
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codes, one per port. The upper 3 bytes are always
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0 and thus ignored.
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- calxeda,pre-clocks : a u32 that indicates the number of additional clock
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cycles to transmit before sending an SGPIO pattern
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- calxeda,post-clocks: a u32 that indicates the number of additional clock
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cycles to transmit after sending an SGPIO pattern
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Example:
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sata@ffe08000 {
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compatible = "calxeda,hb-ahci";
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reg = <0xffe08000 0x1000>;
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interrupts = <115>;
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dma-coherent;
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calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
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&combophy0 2 &combophy0 3>;
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calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
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calxeda,led-order = <4 0 1 2 3>;
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calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
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calxeda,pre-clocks = <10>;
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calxeda,post-clocks = <0>;
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};
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