threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
34 lines
1.0 KiB
C
34 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copied from the kernel sources:
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*
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* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
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* Copyright (C) 2002 Paul Mundt
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*/
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#ifndef __TOOLS_LINUX_ASM_SH_BARRIER_H
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#define __TOOLS_LINUX_ASM_SH_BARRIER_H
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/*
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* A brief note on ctrl_barrier(), the control register write barrier.
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*
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* Legacy SH cores typically require a sequence of 8 nops after
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* modification of a control register in order for the changes to take
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* effect. On newer cores (like the sh4a and sh5) this is accomplished
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* with icbi.
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*
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* Also note that on sh4a in the icbi case we can forego a synco for the
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* write barrier, as it's not necessary for control registers.
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*
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* Historically we have only done this type of barrier for the MMUCR, but
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* it's also necessary for the CCR, so we make it generic here instead.
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*/
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#if defined(__SH4A__) || defined(__SH5__)
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#define mb() __asm__ __volatile__ ("synco": : :"memory")
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#define rmb() mb()
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#define wmb() mb()
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#endif
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#include <asm-generic/barrier.h>
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#endif /* __TOOLS_LINUX_ASM_SH_BARRIER_H */
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