threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
82 lines
2.1 KiB
C
82 lines
2.1 KiB
C
/*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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* Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
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* Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/compiler.h>
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#include <linux/export.h>
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#include <linux/stmp_device.h>
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#define STMP_MODULE_CLKGATE (1 << 30)
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#define STMP_MODULE_SFTRST (1 << 31)
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/*
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* Clear the bit and poll it cleared. This is usually called with
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* a reset address and mask being either SFTRST(bit 31) or CLKGATE
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* (bit 30).
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*/
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static int stmp_clear_poll_bit(void __iomem *addr, u32 mask)
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{
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int timeout = 0x400;
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writel(mask, addr + STMP_OFFSET_REG_CLR);
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udelay(1);
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while ((readl(addr) & mask) && --timeout)
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/* nothing */;
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return !timeout;
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}
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int stmp_reset_block(void __iomem *reset_addr)
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{
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int ret;
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int timeout = 0x400;
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/* clear and poll SFTRST */
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ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST);
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if (unlikely(ret))
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goto error;
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/* clear CLKGATE */
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writel(STMP_MODULE_CLKGATE, reset_addr + STMP_OFFSET_REG_CLR);
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/* set SFTRST to reset the block */
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writel(STMP_MODULE_SFTRST, reset_addr + STMP_OFFSET_REG_SET);
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udelay(1);
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/* poll CLKGATE becoming set */
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while ((!(readl(reset_addr) & STMP_MODULE_CLKGATE)) && --timeout)
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/* nothing */;
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if (unlikely(!timeout))
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goto error;
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/* clear and poll SFTRST */
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ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST);
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if (unlikely(ret))
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goto error;
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/* clear and poll CLKGATE */
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ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_CLKGATE);
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if (unlikely(ret))
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goto error;
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return 0;
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error:
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pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
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return -ETIMEDOUT;
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}
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EXPORT_SYMBOL(stmp_reset_block);
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