threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
136 lines
3.0 KiB
C
136 lines
3.0 KiB
C
/*
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* DDR addressing details and AC timing parameters from JEDEC specs
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*
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* Copyright (C) 2012 Texas Instruments, Inc.
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*
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* Aneesh V <aneesh@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <memory/jedec_ddr.h>
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#include <linux/module.h>
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/* LPDDR2 addressing details from JESD209-2 section 2.4 */
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const struct lpddr2_addressing
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lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
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{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
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{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
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{B4, T_REFI_7_8, T_RFC_90}, /* 256M */
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{B4, T_REFI_7_8, T_RFC_90}, /* 512M */
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{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
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{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
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{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
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{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
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{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
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{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
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};
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EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);
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/* LPDDR2 AC timing parameters from JESD209-2 section 12 */
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const struct lpddr2_timings
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lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
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/* Speed bin 400(200 MHz) */
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[0] = {
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.max_freq = 200000000,
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.min_freq = 10000000,
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.tRPab = 21000,
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.tRCD = 18000,
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.tWR = 15000,
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.tRAS_min = 42000,
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.tRRD = 10000,
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.tWTR = 10000,
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.tXP = 7500,
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.tRTP = 7500,
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.tCKESR = 15000,
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.tDQSCK_max = 5500,
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.tFAW = 50000,
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.tZQCS = 90000,
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.tZQCL = 360000,
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.tZQinit = 1000000,
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.tRAS_max_ns = 70000,
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.tDQSCK_max_derated = 6000,
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},
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/* Speed bin 533(266 MHz) */
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[1] = {
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.max_freq = 266666666,
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.min_freq = 10000000,
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.tRPab = 21000,
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.tRCD = 18000,
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.tWR = 15000,
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.tRAS_min = 42000,
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.tRRD = 10000,
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.tWTR = 7500,
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.tXP = 7500,
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.tRTP = 7500,
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.tCKESR = 15000,
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.tDQSCK_max = 5500,
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.tFAW = 50000,
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.tZQCS = 90000,
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.tZQCL = 360000,
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.tZQinit = 1000000,
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.tRAS_max_ns = 70000,
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.tDQSCK_max_derated = 6000,
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},
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/* Speed bin 800(400 MHz) */
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[2] = {
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.max_freq = 400000000,
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.min_freq = 10000000,
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.tRPab = 21000,
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.tRCD = 18000,
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.tWR = 15000,
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.tRAS_min = 42000,
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.tRRD = 10000,
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.tWTR = 7500,
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.tXP = 7500,
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.tRTP = 7500,
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.tCKESR = 15000,
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.tDQSCK_max = 5500,
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.tFAW = 50000,
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.tZQCS = 90000,
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.tZQCL = 360000,
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.tZQinit = 1000000,
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.tRAS_max_ns = 70000,
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.tDQSCK_max_derated = 6000,
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},
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/* Speed bin 1066(533 MHz) */
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[3] = {
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.max_freq = 533333333,
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.min_freq = 10000000,
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.tRPab = 21000,
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.tRCD = 18000,
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.tWR = 15000,
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.tRAS_min = 42000,
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.tRRD = 10000,
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.tWTR = 7500,
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.tXP = 7500,
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.tRTP = 7500,
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.tCKESR = 15000,
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.tDQSCK_max = 5500,
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.tFAW = 50000,
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.tZQCS = 90000,
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.tZQCL = 360000,
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.tZQinit = 1000000,
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.tRAS_max_ns = 70000,
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.tDQSCK_max_derated = 5620,
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},
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};
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EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);
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const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
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.tRPab = 3,
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.tRCD = 3,
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.tWR = 3,
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.tRASmin = 3,
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.tRRD = 2,
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.tWTR = 2,
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.tXP = 2,
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.tRTP = 2,
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.tCKE = 3,
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.tCKESR = 3,
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.tFAW = 8
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};
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EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);
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