threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
38 lines
1.2 KiB
C
38 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __LINUX_SPI_EEPROM_H
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#define __LINUX_SPI_EEPROM_H
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#include <linux/memory.h>
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/*
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* Put one of these structures in platform_data for SPI EEPROMS handled
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* by the "at25" driver. On SPI, most EEPROMS understand the same core
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* command set. If you need to support EEPROMs that don't yet fit, add
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* flags to support those protocol options. These values all come from
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* the chip datasheets.
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*/
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struct spi_eeprom {
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u32 byte_len;
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char name[10];
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u16 page_size; /* for writes */
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u16 flags;
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#define EE_ADDR1 0x0001 /* 8 bit addrs */
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#define EE_ADDR2 0x0002 /* 16 bit addrs */
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#define EE_ADDR3 0x0004 /* 24 bit addrs */
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#define EE_READONLY 0x0008 /* disallow writes */
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/*
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* Certain EEPROMS have a size that is larger than the number of address
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* bytes would allow (e.g. like M95040 from ST that has 512 Byte size
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* but uses only one address byte (A0 to A7) for addressing.) For
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* the extra address bit (A8, A16 or A24) bit 3 of the instruction byte
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* is used. This instruction bit is normally defined as don't care for
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* other AT25 like chips.
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*/
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#define EE_INSTR_BIT3_IS_ADDR 0x0010
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void *context;
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};
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#endif /* __LINUX_SPI_EEPROM_H */
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