threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
883 lines
28 KiB
C
883 lines
28 KiB
C
/*
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* linux/include/linux/mmc/host.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Host driver specific definitions.
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*/
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#ifndef LINUX_MMC_HOST_H
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#define LINUX_MMC_HOST_H
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#include <linux/sched.h>
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#include <linux/device.h>
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#include <linux/fault-inject.h>
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#include <linux/mmc/core.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/pm.h>
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#include <linux/dma-direction.h>
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struct mmc_ios {
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unsigned int clock; /* clock rate */
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unsigned short vdd;
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/* vdd stores the bit number of the selected voltage range from below. */
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unsigned char bus_mode; /* command output mode */
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#define MMC_BUSMODE_OPENDRAIN 1
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#define MMC_BUSMODE_PUSHPULL 2
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unsigned char chip_select; /* SPI chip select */
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#define MMC_CS_DONTCARE 0
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#define MMC_CS_HIGH 1
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#define MMC_CS_LOW 2
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unsigned char power_mode; /* power supply mode */
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#define MMC_POWER_OFF 0
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#define MMC_POWER_UP 1
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#define MMC_POWER_ON 2
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#define MMC_POWER_UNDEFINED 3
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unsigned char bus_width; /* data bus width */
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#define MMC_BUS_WIDTH_1 0
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#define MMC_BUS_WIDTH_4 2
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#define MMC_BUS_WIDTH_8 3
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unsigned char timing; /* timing specification used */
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#define MMC_TIMING_LEGACY 0
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#define MMC_TIMING_MMC_HS 1
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#define MMC_TIMING_SD_HS 2
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#define MMC_TIMING_UHS_SDR12 3
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#define MMC_TIMING_UHS_SDR25 4
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#define MMC_TIMING_UHS_SDR50 5
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#define MMC_TIMING_UHS_SDR104 6
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#define MMC_TIMING_UHS_DDR50 7
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#define MMC_TIMING_MMC_DDR52 8
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#define MMC_TIMING_MMC_HS200 9
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#define MMC_TIMING_MMC_HS400 10
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unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */
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#define MMC_SIGNAL_VOLTAGE_330 0
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#define MMC_SIGNAL_VOLTAGE_180 1
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#define MMC_SIGNAL_VOLTAGE_120 2
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unsigned char drv_type; /* driver type (A, B, C, D) */
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#define MMC_SET_DRIVER_TYPE_B 0
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#define MMC_SET_DRIVER_TYPE_A 1
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#define MMC_SET_DRIVER_TYPE_C 2
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#define MMC_SET_DRIVER_TYPE_D 3
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bool enhanced_strobe; /* hs400es selection */
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};
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#ifdef CONFIG_MTK_EMMC_HW_CQ
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struct mmc_cmdq_host_ops {
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int (*init)(struct mmc_host *host);
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int (*enable)(struct mmc_host *host);
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void (*disable)(struct mmc_host *host, bool soft);
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int (*request)(struct mmc_host *host, struct mmc_request *mrq);
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void (*post_req)(struct mmc_host *host, int tag, int err);
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int (*halt)(struct mmc_host *host, bool halt);
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void (*reset)(struct mmc_host *host, bool soft);
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void (*dumpstate)(struct mmc_host *host, bool more);
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};
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#endif
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struct mmc_host;
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struct mmc_host_ops {
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/*
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* It is optional for the host to implement pre_req and post_req in
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* order to support double buffering of requests (prepare one
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* request while another request is active).
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* pre_req() must always be followed by a post_req().
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* To undo a call made to pre_req(), call post_req() with
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* a nonzero err condition.
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*/
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void (*post_req)(struct mmc_host *host, struct mmc_request *req,
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int err);
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void (*pre_req)(struct mmc_host *host, struct mmc_request *req);
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void (*request)(struct mmc_host *host, struct mmc_request *req);
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/*
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* Avoid calling the next three functions too often or in a "fast
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* path", since underlaying controller might implement them in an
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* expensive and/or slow way. Also note that these functions might
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* sleep, so don't call them in the atomic contexts!
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*/
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/*
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* Notes to the set_ios callback:
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* ios->clock might be 0. For some controllers, setting 0Hz
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* as any other frequency works. However, some controllers
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* explicitly need to disable the clock. Otherwise e.g. voltage
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* switching might fail because the SDCLK is not really quiet.
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*/
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void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios);
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/*
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* Return values for the get_ro callback should be:
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* 0 for a read/write card
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* 1 for a read-only card
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* -ENOSYS when not supported (equal to NULL callback)
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* or a negative errno value when something bad happened
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*/
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int (*get_ro)(struct mmc_host *host);
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/*
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* Return values for the get_cd callback should be:
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* 0 for a absent card
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* 1 for a present card
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* -ENOSYS when not supported (equal to NULL callback)
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* or a negative errno value when something bad happened
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*/
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int (*get_cd)(struct mmc_host *host);
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void (*enable_sdio_irq)(struct mmc_host *host, int enable);
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void (*ack_sdio_irq)(struct mmc_host *host);
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/* optional callback for HC quirks */
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void (*init_card)(struct mmc_host *host, struct mmc_card *card);
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int (*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios);
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/* Check if the card is pulling dat[0:3] low */
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int (*card_busy)(struct mmc_host *host);
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/* The tuning command opcode value is different for SD and eMMC cards */
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int (*execute_tuning)(struct mmc_host *host, u32 opcode);
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/* Prepare HS400 target operating frequency depending host driver */
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int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios);
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/* Prepare enhanced strobe depending host driver */
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void (*hs400_enhanced_strobe)(struct mmc_host *host,
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struct mmc_ios *ios);
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int (*select_drive_strength)(struct mmc_card *card,
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unsigned int max_dtr, int host_drv,
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int card_drv, int *drv_type);
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void (*hw_reset)(struct mmc_host *host);
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void (*card_event)(struct mmc_host *host);
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void (*remove_bad_sdcard)(struct mmc_host *host);
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/*
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* Optional callback to support controllers with HW issues for multiple
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* I/O. Returns the number of supported blocks for the request.
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*/
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int (*multi_io_quirk)(struct mmc_card *card,
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unsigned int direction, int blk_size);
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};
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struct mmc_cqe_ops {
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/* Allocate resources, and make the CQE operational */
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int (*cqe_enable)(struct mmc_host *host, struct mmc_card *card);
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/* Free resources, and make the CQE non-operational */
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void (*cqe_disable)(struct mmc_host *host);
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/*
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* Issue a read, write or DCMD request to the CQE. Also deal with the
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* effect of ->cqe_off().
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*/
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int (*cqe_request)(struct mmc_host *host, struct mmc_request *mrq);
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/* Free resources (e.g. DMA mapping) associated with the request */
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void (*cqe_post_req)(struct mmc_host *host, struct mmc_request *mrq);
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/*
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* Prepare the CQE and host controller to accept non-CQ commands. There
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* is no corresponding ->cqe_on(), instead ->cqe_request() is required
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* to deal with that.
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*/
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void (*cqe_off)(struct mmc_host *host);
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/*
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* Wait for all CQE tasks to complete. Return an error if recovery
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* becomes necessary.
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*/
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int (*cqe_wait_for_idle)(struct mmc_host *host);
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/*
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* Notify CQE that a request has timed out. Return false if the request
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* completed or true if a timeout happened in which case indicate if
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* recovery is needed.
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*/
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bool (*cqe_timeout)(struct mmc_host *host, struct mmc_request *mrq,
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bool *recovery_needed);
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/*
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* Stop all CQE activity and prepare the CQE and host controller to
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* accept recovery commands.
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*/
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void (*cqe_recovery_start)(struct mmc_host *host);
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/*
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* Clear the queue and call mmc_cqe_request_done() on all requests.
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* Requests that errored will have the error set on the mmc_request
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* (data->error or cmd->error for DCMD). Requests that did not error
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* will have zero data bytes transferred.
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*/
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void (*cqe_recovery_finish)(struct mmc_host *host);
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};
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#ifdef CONFIG_MTK_EMMC_HW_CQ
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struct mmc_cmdq_req {
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unsigned int cmd_flags;
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u32 blk_addr;
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/* active mmc request */
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struct mmc_request mrq;
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struct mmc_data data;
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struct mmc_command cmd;
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#define DCMD (1 << 0)
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#define QBR (1 << 1)
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#define DIR (1 << 2)
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#define PRIO (1 << 3)
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#define REL_WR (1 << 4)
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#define DAT_TAG (1 << 5)
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#define FORCED_PRG (1 << 6)
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unsigned int cmdq_req_flags;
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unsigned int resp_idx;
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unsigned int resp_arg;
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unsigned int dev_pend_tasks;
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bool resp_err;
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bool skip_err_handling;
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bool skip_dump; /* for skip dump info */
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bool skip_reset; /* for skip autok */
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int tag; /* used for command queuing */
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u8 ctx_id;
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};
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#endif
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struct keyslot_mgmt_ll_ops;
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struct mmc_crypto_variant_ops {
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void (*setup_rq_keyslot_manager)(struct mmc_host *host,
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struct request_queue *q);
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void (*destroy_rq_keyslot_manager)(struct mmc_host *host,
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struct request_queue *q);
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int (*init_crypto)(struct mmc_host *host,
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const struct keyslot_mgmt_ll_ops *ksm_ops);
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void (*enable)(struct mmc_host *host);
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void (*disable)(struct mmc_host *host);
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int (*suspend)(struct mmc_host *host);
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int (*resume)(struct mmc_host *host);
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int (*debug)(struct mmc_host *host);
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void (*host_init_crypto)(struct mmc_host *host);
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int (*get_crypto_capabilities)(struct mmc_host *host);
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int (*prepare_mqr_crypto)(struct mmc_host *host,
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u64 data_unit_num, int ddir, int slot);
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void (*host_program_key)(struct mmc_host *host,
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u32 *key, u32 *tkey, u32 config);
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int (*complete_mqr_crypto)(struct mmc_host *host);
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void (*msdc_crypto_keyslot_evict)(struct mmc_host *host);
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void *priv;
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};
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struct mmc_async_req {
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/* active mmc request */
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struct mmc_request *mrq;
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#ifdef CONFIG_MTK_EMMC_CQ_SUPPORT
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struct mmc_request *mrq_que;
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#endif
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/*
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* Check error status of completed mmc request.
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* Returns 0 if success otherwise non zero.
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*/
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enum mmc_blk_status (*err_check)(struct mmc_card *, struct mmc_async_req *);
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#ifdef CONFIG_MTK_EMMC_CQ_SUPPORT
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#define MMC_QUEUE_BEFORE_ENQ (0) /* mrq is entered in driver */
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#define MMC_QUEUE_ENQ (1) /* mrq is enqueued in device */
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#define MMC_QUEUE_BEFORE_QRDY (2) /* mrq is 44/45 issue & wait for qrdy */
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/* mrq is checking qrdy & ready to transfer */
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#define MMC_QUEUE_BEFORE_TRAN (3)
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#define MMC_QUEUE_TRAN (4) /* mrq is transfer */
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/* mrq is transfer done & cheking busy in case of write */
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#define MMC_QUEUE_BUSY (5)
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/* mrq is terminated transfer
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* including busy check & ready to post process
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*/
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#define MMC_QUEUE_BEFORE_POST (7)
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unsigned long state;
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unsigned int prio;
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#endif
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};
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/**
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* struct mmc_slot - MMC slot functions
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*
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* @cd_irq: MMC/SD-card slot hotplug detection IRQ or -EINVAL
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* @handler_priv: MMC/SD-card slot context
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*
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* Some MMC/SD host controllers implement slot-functions like card and
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* write-protect detection natively. However, a large number of controllers
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* leave these functions to the CPU. This struct provides a hook to attach
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* such slot-function drivers.
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*/
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struct mmc_slot {
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int cd_irq;
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bool cd_wake_enabled;
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void *handler_priv;
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};
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#ifdef CONFIG_MTK_EMMC_HW_CQ
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/**
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* mmc_cmdq_context_info - describes the contexts of cmdq
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* @active_reqs requests being processed
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* @data_active_reqs data requests being processed
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* @curr_state state of cmdq engine
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* @cmdq_ctx_lock acquire this before accessing this structure
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* @queue_empty_wq workqueue for waiting for all
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* the outstanding requests to be completed
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* @wait waiting for all conditions described in
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* mmc_cmdq_ready_wait to be satisified before
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* issuing the new request to LLD.
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* @err_rwsem synchronizes issue/completion/error-handler ctx
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*/
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struct mmc_cmdq_context_info {
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unsigned long active_reqs; /* in-flight requests */
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unsigned long data_active_reqs; /* in-flight data requests */
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unsigned long curr_state;
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#define CMDQ_STATE_ERR 0
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#define CMDQ_STATE_DCMD_ACTIVE 1
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#define CMDQ_STATE_HALT 2
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#define CMDQ_STATE_CQ_DISABLE 3
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#define CMDQ_STATE_REQ_TIMED_OUT 4
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wait_queue_head_t queue_empty_wq;
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wait_queue_head_t wait;
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int active_small_sector_read_reqs;
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struct rw_semaphore err_rwsem;
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};
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#endif
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/**
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* mmc_context_info - synchronization details for mmc context
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* @is_done_rcv wake up reason was done request
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* @is_new_req wake up reason was new request
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* @is_waiting_last_req mmc context waiting for single running request
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* @wait wait queue
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*/
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struct mmc_context_info {
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bool is_done_rcv;
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bool is_new_req;
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bool is_waiting_last_req;
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wait_queue_head_t wait;
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};
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#ifdef CONFIG_MTK_EMMC_CQ_SUPPORT
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#define EMMC_MAX_QUEUE_DEPTH (32)
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#define EMMC_MIN_RT_CLASS_TAG_COUNT (4)
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#endif
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struct regulator;
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struct mmc_pwrseq;
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struct mmc_supply {
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struct regulator *vmmc; /* Card power supply */
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struct regulator *vqmmc; /* Optional Vccq supply */
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};
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/* CCAP - Crypto Capability 100h */
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union swcqhci_crypto_capabilities {
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__le32 reg_val;
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struct {
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u8 num_crypto_cap;
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u8 config_count;
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u8 reserved;
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u8 config_array_ptr;
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};
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};
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enum swcqhci_crypto_key_size {
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SWCQHCI_CRYPTO_KEY_SIZE_128 = 0,
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SWCQHCI_CRYPTO_KEY_SIZE_192 = 1,
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SWCQHCI_CRYPTO_KEY_SIZE_256 = 2,
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SWCQHCI_CRYPTO_KEY_SIZE_512 = 3,
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SWCQHCI_CRYPTO_KEY_SIZE_INVALID = 4,
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};
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enum swcqhci_crypto_alg {
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SWCQHCI_CRYPTO_ALG_AES_XTS = 4,
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SWCQHCI_CRYPTO_ALG_BITLOCKER_AES_CBC = 3,
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SWCQHCI_CRYPTO_ALG_AES_ECB = 2,
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SWCQHCI_CRYPTO_ALG_ESSIV_AES_CBC = 1,
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SWCQHCI_CRYPTO_ALG_INVALID = 0,
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};
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/* x-CRYPTOCAP - Crypto Capability X */
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union swcqhci_crypto_cap_entry {
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__le32 reg_val;
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struct {
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u8 algorithm_id;
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u8 sdus_mask; /* Supported data unit size mask */
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u8 key_size;
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u8 reserved;
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};
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};
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/* Please note that enable bit @ bit15 for spec */
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#define MMC_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
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#define MMC_CRYPTO_KEY_MAX_SIZE 64
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/* x-CRYPTOCFG - Crypto Configuration X */
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/* key info will be fill in here, find slot will use, # of array == # of slot */
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union swcqhci_crypto_cfg_entry {
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__le32 reg_val[32];
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struct {
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u8 crypto_key[MMC_CRYPTO_KEY_MAX_SIZE];
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/* 4KB/512 = 8 */
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u8 data_unit_size;
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u8 crypto_cap_idx;
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u8 reserved_1;
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u8 config_enable;
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u8 reserved_multi_host;
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u8 reserved_2;
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u8 vsb[2];
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u8 reserved_3[56];
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};
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};
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struct mmc_host {
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struct device *parent;
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struct device class_dev;
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int index;
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const struct mmc_host_ops *ops;
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struct mmc_pwrseq *pwrseq;
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unsigned int f_min;
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unsigned int f_max;
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unsigned int f_init;
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u32 ocr_avail;
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u32 ocr_avail_sdio; /* SDIO-specific OCR */
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u32 ocr_avail_sd; /* SD-specific OCR */
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u32 ocr_avail_mmc; /* MMC-specific OCR */
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#ifdef CONFIG_PM_SLEEP
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struct notifier_block pm_notify;
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#endif
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u32 max_current_330;
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u32 max_current_300;
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u32 max_current_180;
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#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
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#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
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#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
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#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
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#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
|
|
#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
|
|
#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
|
|
#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
|
|
#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
|
|
#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
|
|
#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
|
|
#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
|
|
#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
|
|
#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
|
|
#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
|
|
#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
|
|
#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
|
|
|
|
u32 caps; /* Host capabilities */
|
|
|
|
#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */
|
|
#define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */
|
|
#define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */
|
|
#define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */
|
|
#define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */
|
|
#define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */
|
|
#define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */
|
|
#define MMC_CAP_AGGRESSIVE_PM (1 << 7) /* Suspend (e)MMC/SD at idle */
|
|
#define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */
|
|
#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */
|
|
#define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */
|
|
#define MMC_CAP_3_3V_DDR (1 << 11) /* Host supports eMMC DDR 3.3V */
|
|
#define MMC_CAP_1_8V_DDR (1 << 12) /* Host supports eMMC DDR 1.8V */
|
|
#define MMC_CAP_1_2V_DDR (1 << 13) /* Host supports eMMC DDR 1.2V */
|
|
#define MMC_CAP_POWER_OFF_CARD (1 << 14) /* Can power off after boot */
|
|
#define MMC_CAP_BUS_WIDTH_TEST (1 << 15) /* CMD14/CMD19 bus width ok */
|
|
#define MMC_CAP_UHS_SDR12 (1 << 16) /* Host supports UHS SDR12 mode */
|
|
#define MMC_CAP_UHS_SDR25 (1 << 17) /* Host supports UHS SDR25 mode */
|
|
#define MMC_CAP_UHS_SDR50 (1 << 18) /* Host supports UHS SDR50 mode */
|
|
#define MMC_CAP_UHS_SDR104 (1 << 19) /* Host supports UHS SDR104 mode */
|
|
#define MMC_CAP_UHS_DDR50 (1 << 20) /* Host supports UHS DDR50 mode */
|
|
/* (1 << 21) is free for reuse */
|
|
#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */
|
|
#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */
|
|
#define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */
|
|
#define MMC_CAP_CD_WAKE (1 << 28) /* Enable card detect wake */
|
|
#define MMC_CAP_CMD_DURING_TFR (1 << 29) /* Commands during data transfer */
|
|
#define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */
|
|
#define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */
|
|
|
|
u32 caps2; /* More host capabilities */
|
|
|
|
#define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */
|
|
#define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) /* Can do full power cycle */
|
|
#define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */
|
|
#define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */
|
|
#define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \
|
|
MMC_CAP2_HS200_1_2V_SDR)
|
|
#define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */
|
|
#define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */
|
|
#define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */
|
|
#define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */
|
|
#define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */
|
|
#define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \
|
|
MMC_CAP2_HS400_1_2V)
|
|
#define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)
|
|
#define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
|
|
#define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */
|
|
#define MMC_CAP2_NO_SDIO (1 << 19) /* Do not send SDIO commands during initialization */
|
|
#define MMC_CAP2_HS400_ES (1 << 20) /* Host supports enhanced strobe */
|
|
#define MMC_CAP2_NO_SD (1 << 21) /* Do not send SD commands during initialization */
|
|
#define MMC_CAP2_NO_MMC (1 << 22) /* Do not send (e)MMC commands during initialization */
|
|
#define MMC_CAP2_CQE (1 << 23) /* Has eMMC command queue engine */
|
|
#define MMC_CAP2_CQE_DCMD (1 << 24) /* CQE can issue a direct command */
|
|
#define MMC_CAP2_NMCARD (1 << 26)
|
|
#define MMC_CAP2_CRYPTO (1 << 27) /* Host supports inline encryption */
|
|
|
|
mmc_pm_flag_t pm_caps; /* supported pm features */
|
|
|
|
/* host specific block data */
|
|
unsigned int max_seg_size; /* see blk_queue_max_segment_size */
|
|
unsigned short max_segs; /* see blk_queue_max_segments */
|
|
unsigned short unused;
|
|
unsigned int max_req_size; /* maximum number of bytes in one req */
|
|
unsigned int max_blk_size; /* maximum size of one mmc block */
|
|
unsigned int max_blk_count; /* maximum number of blocks in one req */
|
|
unsigned int max_busy_timeout; /* max busy timeout in ms */
|
|
|
|
/* private data */
|
|
spinlock_t lock; /* lock for claim and bus ops */
|
|
|
|
struct mmc_ios ios; /* current io bus settings */
|
|
struct mmc_ios cached_ios;
|
|
|
|
/* group bitfields together to minimize padding */
|
|
unsigned int use_spi_crc:1;
|
|
unsigned int claimed:1; /* host exclusively claimed */
|
|
unsigned int bus_dead:1; /* bus has been released */
|
|
unsigned int can_retune:1; /* re-tuning can be used */
|
|
unsigned int doing_retune:1; /* re-tuning in progress */
|
|
unsigned int retune_now:1; /* do re-tuning at next req */
|
|
unsigned int retune_paused:1; /* re-tuning is temporarily disabled */
|
|
|
|
int rescan_disable; /* disable card detection */
|
|
int rescan_entered; /* used with nonremovable devices */
|
|
|
|
int need_retune; /* re-tuning is needed */
|
|
int hold_retune; /* hold off re-tuning */
|
|
unsigned int retune_period; /* re-tuning period in secs */
|
|
struct timer_list retune_timer; /* for periodic re-tuning */
|
|
|
|
bool trigger_card_event; /* card_event necessary */
|
|
|
|
struct mmc_card *card; /* device attached to this host */
|
|
|
|
wait_queue_head_t wq;
|
|
struct task_struct *claimer; /* task that has host claimed */
|
|
int claim_cnt; /* "claim" nesting count */
|
|
|
|
struct delayed_work detect;
|
|
int detect_change; /* card detect flag */
|
|
struct mmc_slot slot;
|
|
|
|
const struct mmc_bus_ops *bus_ops; /* current bus driver */
|
|
unsigned int bus_refs; /* reference counter */
|
|
|
|
unsigned int sdio_irqs;
|
|
struct task_struct *sdio_irq_thread;
|
|
struct delayed_work sdio_irq_work;
|
|
bool sdio_irq_pending;
|
|
atomic_t sdio_irq_thread_abort;
|
|
|
|
mmc_pm_flag_t pm_flags; /* requested pm features */
|
|
|
|
struct led_trigger *led; /* activity led */
|
|
|
|
#ifdef CONFIG_REGULATOR
|
|
bool regulator_enabled; /* regulator state */
|
|
#endif
|
|
struct mmc_supply supply;
|
|
|
|
struct dentry *debugfs_root;
|
|
|
|
struct mmc_async_req *areq; /* active async req */
|
|
struct mmc_context_info context_info; /* async synchronization info */
|
|
|
|
/* Ongoing data transfer that allows commands during transfer */
|
|
struct mmc_request *ongoing_mrq;
|
|
|
|
#ifdef CONFIG_MTK_EMMC_CQ_SUPPORT
|
|
struct mmc_async_req *areq_que[EMMC_MAX_QUEUE_DEPTH];
|
|
struct mmc_async_req *areq_cur;
|
|
atomic_t areq_cnt;
|
|
|
|
spinlock_t cmd_que_lock;
|
|
spinlock_t dat_que_lock;
|
|
spinlock_t que_lock;
|
|
struct list_head cmd_que;
|
|
struct list_head dat_que;
|
|
|
|
unsigned long state;
|
|
wait_queue_head_t cmp_que;
|
|
wait_queue_head_t cmdq_que;
|
|
struct mmc_request *done_mrq;
|
|
struct mmc_command chk_cmd;
|
|
struct mmc_request chk_mrq;
|
|
struct mmc_command que_cmd;
|
|
struct mmc_request que_mrq;
|
|
struct mmc_command deq_cmd;
|
|
struct mmc_request deq_mrq;
|
|
|
|
struct mmc_queue_req *mqrq_cur;
|
|
struct mmc_queue_req *mqrq_prev;
|
|
struct mmc_request *prev_mrq;
|
|
|
|
struct task_struct *cmdq_thread;
|
|
atomic_t cq_rw;
|
|
atomic_t cq_w;
|
|
unsigned int wp_error;
|
|
atomic_t cq_wait_rdy;
|
|
atomic_t cq_rdy_cnt;
|
|
unsigned long task_id_index;
|
|
int cur_rw_task;
|
|
#define CQ_TASK_IDLE 99
|
|
|
|
atomic_t is_data_dma;
|
|
atomic_t cq_tuning_now;
|
|
#ifdef CONFIG_MMC_FFU
|
|
atomic_t stop_queue;
|
|
#endif
|
|
unsigned int data_mrq_queued[32];
|
|
unsigned int cmdq_support_changed;
|
|
int align_size;
|
|
#endif
|
|
|
|
#ifdef CONFIG_FAIL_MMC_REQUEST
|
|
struct fault_attr fail_mmc_request;
|
|
#endif
|
|
|
|
unsigned int actual_clock; /* Actual HC clock rate */
|
|
|
|
unsigned int slotno; /* used for sdio acpi binding */
|
|
|
|
int dsr_req; /* DSR value is valid */
|
|
u32 dsr; /* optional driver stage (DSR) value */
|
|
|
|
/* Command Queue Engine (CQE) support */
|
|
const struct mmc_cqe_ops *cqe_ops;
|
|
void *cqe_private;
|
|
int cqe_qdepth;
|
|
bool cqe_enabled;
|
|
bool cqe_on;
|
|
|
|
#ifdef CONFIG_MTK_EMMC_HW_CQ
|
|
const struct mmc_cmdq_host_ops *cmdq_ops;
|
|
struct mmc_cmdq_context_info cmdq_ctx;
|
|
int num_cq_slots;
|
|
int dcmd_cq_slot;
|
|
bool cmdq_thist_enabled;
|
|
/*
|
|
* several cmdq supporting host controllers are extensions
|
|
* of legacy controllers. This variable can be used to store
|
|
* a reference to the cmdq extension of the existing host
|
|
* controller.
|
|
*/
|
|
void *cmdq_private;
|
|
struct mmc_request *err_mrq;
|
|
#endif
|
|
|
|
#ifdef CONFIG_MMC_CRYPTO
|
|
/* crypto */
|
|
const struct mmc_crypto_variant_ops *crypto_vops;
|
|
union swcqhci_crypto_capabilities crypto_capabilities;
|
|
union swcqhci_crypto_cap_entry *crypto_cap_array;
|
|
u8 crypto_cfg_register;
|
|
union swcqhci_crypto_cfg_entry *crypto_cfgs;
|
|
struct keyslot_manager *ksm;
|
|
#endif /* CONFIG_MMC_CRYPTO */
|
|
|
|
|
|
#ifdef CONFIG_MMC_EMBEDDED_SDIO
|
|
struct {
|
|
struct sdio_cis *cis;
|
|
struct sdio_cccr *cccr;
|
|
struct sdio_embedded_func *funcs;
|
|
int num_funcs;
|
|
} embedded_sdio_data;
|
|
#endif
|
|
unsigned long private[0] ____cacheline_aligned;
|
|
};
|
|
|
|
struct device_node;
|
|
|
|
struct mmc_host *mmc_alloc_host(int extra, struct device *);
|
|
int mmc_add_host(struct mmc_host *);
|
|
void mmc_remove_host(struct mmc_host *);
|
|
void mmc_free_host(struct mmc_host *);
|
|
int mmc_of_parse(struct mmc_host *host);
|
|
int mmc_of_parse_voltage(struct device_node *np, u32 *mask);
|
|
|
|
#ifdef CONFIG_MMC_EMBEDDED_SDIO
|
|
extern void mmc_set_embedded_sdio_data(struct mmc_host *host,
|
|
struct sdio_cis *cis,
|
|
struct sdio_cccr *cccr,
|
|
struct sdio_embedded_func *funcs,
|
|
int num_funcs);
|
|
#endif
|
|
|
|
static inline void *mmc_priv(struct mmc_host *host)
|
|
{
|
|
return (void *)host->private;
|
|
}
|
|
|
|
#ifdef CONFIG_MTK_EMMC_HW_CQ
|
|
static inline void *mmc_cmdq_private(struct mmc_host *host)
|
|
{
|
|
return host->cmdq_private;
|
|
}
|
|
#endif
|
|
|
|
#define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI)
|
|
|
|
#define mmc_dev(x) ((x)->parent)
|
|
#define mmc_classdev(x) (&(x)->class_dev)
|
|
#define mmc_hostname(x) (dev_name(&(x)->class_dev))
|
|
|
|
int mmc_power_save_host(struct mmc_host *host);
|
|
int mmc_power_restore_host(struct mmc_host *host);
|
|
|
|
void mmc_detect_change(struct mmc_host *, unsigned long delay);
|
|
void mmc_request_done(struct mmc_host *, struct mmc_request *);
|
|
void mmc_command_done(struct mmc_host *host, struct mmc_request *mrq);
|
|
|
|
#ifdef CONFIG_MTK_EMMC_CQ_SUPPORT
|
|
int mmc_blk_end_queued_req(struct mmc_host *host,
|
|
struct mmc_async_req *areq_active, int index, int status);
|
|
/* add for emmc reset when error happen */
|
|
extern int current_mmc_part_type;
|
|
extern int emmc_resetting_when_cmdq;
|
|
#endif
|
|
|
|
static inline void mmc_signal_sdio_irq(struct mmc_host *host)
|
|
{
|
|
host->ops->enable_sdio_irq(host, 0);
|
|
host->sdio_irq_pending = true;
|
|
if (host->sdio_irq_thread)
|
|
wake_up_process(host->sdio_irq_thread);
|
|
}
|
|
|
|
void sdio_run_irqs(struct mmc_host *host);
|
|
void sdio_signal_irq(struct mmc_host *host);
|
|
|
|
#ifdef CONFIG_REGULATOR
|
|
int mmc_regulator_get_ocrmask(struct regulator *supply);
|
|
int mmc_regulator_set_ocr(struct mmc_host *mmc,
|
|
struct regulator *supply,
|
|
unsigned short vdd_bit);
|
|
int mmc_regulator_set_vqmmc(struct mmc_host *mmc, struct mmc_ios *ios);
|
|
#else
|
|
static inline int mmc_regulator_get_ocrmask(struct regulator *supply)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int mmc_regulator_set_ocr(struct mmc_host *mmc,
|
|
struct regulator *supply,
|
|
unsigned short vdd_bit)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline int mmc_regulator_set_vqmmc(struct mmc_host *mmc,
|
|
struct mmc_ios *ios)
|
|
{
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max);
|
|
int mmc_regulator_get_supply(struct mmc_host *mmc);
|
|
|
|
static inline int mmc_card_is_removable(struct mmc_host *host)
|
|
{
|
|
return !(host->caps & MMC_CAP_NONREMOVABLE);
|
|
}
|
|
|
|
static inline int mmc_card_keep_power(struct mmc_host *host)
|
|
{
|
|
return host->pm_flags & MMC_PM_KEEP_POWER;
|
|
}
|
|
|
|
static inline int mmc_card_wake_sdio_irq(struct mmc_host *host)
|
|
{
|
|
return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ;
|
|
}
|
|
|
|
#ifdef CONFIG_MTK_EMMC_HW_CQ
|
|
static inline void mmc_host_set_halt(struct mmc_host *host)
|
|
{
|
|
set_bit(CMDQ_STATE_HALT, &host->cmdq_ctx.curr_state);
|
|
}
|
|
|
|
static inline void mmc_host_clr_halt(struct mmc_host *host)
|
|
{
|
|
clear_bit(CMDQ_STATE_HALT, &host->cmdq_ctx.curr_state);
|
|
}
|
|
|
|
static inline int mmc_host_halt(struct mmc_host *host)
|
|
{
|
|
return test_bit(CMDQ_STATE_HALT, &host->cmdq_ctx.curr_state);
|
|
}
|
|
|
|
static inline void mmc_host_set_cq_disable(struct mmc_host *host)
|
|
{
|
|
set_bit(CMDQ_STATE_CQ_DISABLE, &host->cmdq_ctx.curr_state);
|
|
}
|
|
|
|
static inline void mmc_host_clr_cq_disable(struct mmc_host *host)
|
|
{
|
|
clear_bit(CMDQ_STATE_CQ_DISABLE, &host->cmdq_ctx.curr_state);
|
|
}
|
|
|
|
static inline int mmc_host_cq_disable(struct mmc_host *host)
|
|
{
|
|
return test_bit(CMDQ_STATE_CQ_DISABLE, &host->cmdq_ctx.curr_state);
|
|
}
|
|
#endif
|
|
|
|
/* TODO: Move to private header */
|
|
static inline int mmc_card_hs(struct mmc_card *card)
|
|
{
|
|
return card->host->ios.timing == MMC_TIMING_SD_HS ||
|
|
card->host->ios.timing == MMC_TIMING_MMC_HS;
|
|
}
|
|
|
|
/* TODO: Move to private header */
|
|
static inline int mmc_card_uhs(struct mmc_card *card)
|
|
{
|
|
return card->host->ios.timing >= MMC_TIMING_UHS_SDR12 &&
|
|
card->host->ios.timing <= MMC_TIMING_UHS_DDR50;
|
|
}
|
|
|
|
void mmc_retune_timer_stop(struct mmc_host *host);
|
|
|
|
static inline void mmc_retune_needed(struct mmc_host *host)
|
|
{
|
|
if (host->can_retune)
|
|
host->need_retune = 1;
|
|
}
|
|
|
|
static inline bool mmc_can_retune(struct mmc_host *host)
|
|
{
|
|
return host->can_retune == 1;
|
|
}
|
|
|
|
static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data)
|
|
{
|
|
return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
|
|
}
|
|
|
|
int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error);
|
|
int mmc_abort_tuning(struct mmc_host *host, u32 opcode);
|
|
|
|
#endif /* LINUX_MMC_HOST_H */
|