threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
67 lines
1.7 KiB
C
67 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* sp5100_tco: TCO timer driver for sp5100 chipsets.
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*
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* (c) Copyright 2009 Google Inc., All Rights Reserved.
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*
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* TCO timer driver for sp5100 chipsets
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*/
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/*
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* Some address definitions for the Watchdog
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*/
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#define SP5100_WDT_MEM_MAP_SIZE 0x08
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#define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */
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#define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */
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#define SP5100_WDT_START_STOP_BIT (1 << 0)
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#define SP5100_WDT_TRIGGER_BIT (1 << 7)
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#define SP5100_PM_IOPORTS_SIZE 0x02
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/*
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* These two IO registers are hardcoded and there doesn't seem to be a way to
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* read them from a register.
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*/
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/* For SP5100/SB7x0 chipset */
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#define SP5100_IO_PM_INDEX_REG 0xCD6
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#define SP5100_IO_PM_DATA_REG 0xCD7
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#define SP5100_SB_RESOURCE_MMIO_BASE 0x9C
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#define SP5100_PM_WATCHDOG_CONTROL 0x69
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#define SP5100_PM_WATCHDOG_BASE 0x6C
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#define SP5100_PM_WATCHDOG_FIRED (1 << 1)
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#define SP5100_PM_WATCHDOG_ACTION_RESET (1 << 2)
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#define SP5100_PCI_WATCHDOG_MISC_REG 0x41
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#define SP5100_PCI_WATCHDOG_DECODE_EN (1 << 3)
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#define SP5100_PM_WATCHDOG_DISABLE (1 << 0)
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#define SP5100_PM_WATCHDOG_SECOND_RES (3 << 1)
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#define SP5100_DEVNAME "SP5100 TCO"
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/* For SB8x0(or later) chipset */
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#define SB800_IO_PM_INDEX_REG 0xCD6
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#define SB800_IO_PM_DATA_REG 0xCD7
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#define SB800_PM_ACPI_MMIO_EN 0x24
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#define SB800_PM_WATCHDOG_CONTROL 0x48
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#define SB800_PM_WATCHDOG_BASE 0x48
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#define SB800_PM_WATCHDOG_CONFIG 0x4C
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#define SB800_PCI_WATCHDOG_DECODE_EN (1 << 0)
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#define SB800_PM_WATCHDOG_DISABLE (1 << 1)
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#define SB800_PM_WATCHDOG_SECOND_RES (3 << 0)
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#define SB800_ACPI_MMIO_DECODE_EN (1 << 0)
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#define SB800_ACPI_MMIO_SEL (1 << 1)
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#define SB800_PM_WDT_MMIO_OFFSET 0xB00
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#define SB800_DEVNAME "SB800 TCO"
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