threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
109 lines
2.6 KiB
C
109 lines
2.6 KiB
C
/*
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* Copyright (C) Maxime Coquelin 2015
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* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
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* License terms: GNU General Public License (GPL), version 2
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*
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* Heavily based on sunxi driver from Maxime Ripard.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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struct stm32_reset_data {
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spinlock_t lock;
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void __iomem *membase;
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struct reset_controller_dev rcdev;
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};
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static int stm32_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct stm32_reset_data *data = container_of(rcdev,
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struct stm32_reset_data,
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rcdev);
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int bank = id / BITS_PER_LONG;
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int offset = id % BITS_PER_LONG;
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&data->lock, flags);
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reg = readl(data->membase + (bank * 4));
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writel(reg | BIT(offset), data->membase + (bank * 4));
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spin_unlock_irqrestore(&data->lock, flags);
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return 0;
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}
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static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct stm32_reset_data *data = container_of(rcdev,
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struct stm32_reset_data,
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rcdev);
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int bank = id / BITS_PER_LONG;
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int offset = id % BITS_PER_LONG;
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&data->lock, flags);
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reg = readl(data->membase + (bank * 4));
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writel(reg & ~BIT(offset), data->membase + (bank * 4));
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spin_unlock_irqrestore(&data->lock, flags);
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return 0;
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}
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static const struct reset_control_ops stm32_reset_ops = {
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.assert = stm32_reset_assert,
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.deassert = stm32_reset_deassert,
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};
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static const struct of_device_id stm32_reset_dt_ids[] = {
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{ .compatible = "st,stm32-rcc", },
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{ /* sentinel */ },
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};
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static int stm32_reset_probe(struct platform_device *pdev)
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{
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struct stm32_reset_data *data;
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struct resource *res;
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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data->membase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(data->membase))
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return PTR_ERR(data->membase);
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spin_lock_init(&data->lock);
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data->rcdev.owner = THIS_MODULE;
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data->rcdev.nr_resets = resource_size(res) * 8;
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data->rcdev.ops = &stm32_reset_ops;
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data->rcdev.of_node = pdev->dev.of_node;
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return devm_reset_controller_register(&pdev->dev, &data->rcdev);
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}
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static struct platform_driver stm32_reset_driver = {
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.probe = stm32_reset_probe,
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.driver = {
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.name = "stm32-rcc-reset",
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.of_match_table = stm32_reset_dt_ids,
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},
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};
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builtin_platform_driver(stm32_reset_driver);
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