threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
108 lines
3.1 KiB
C
108 lines
3.1 KiB
C
/*
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* Applied Micro X-Gene SoC Ethernet v2 Driver
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*
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* Copyright (c) 2017, Applied Micro Circuits Corporation
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* Author(s): Iyappan Subramanian <isubramanian@apm.com>
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* Keyur Chudgar <kchudgar@apm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __XGENE_ENET_V2_MAC_H__
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#define __XGENE_ENET_V2_MAC_H__
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/* Register offsets */
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#define MAC_CONFIG_1 0xa000
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#define MAC_CONFIG_2 0xa004
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#define MII_MGMT_CONFIG 0xa020
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#define MII_MGMT_COMMAND 0xa024
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#define MII_MGMT_ADDRESS 0xa028
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#define MII_MGMT_CONTROL 0xa02c
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#define MII_MGMT_STATUS 0xa030
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#define MII_MGMT_INDICATORS 0xa034
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#define INTERFACE_CONTROL 0xa038
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#define STATION_ADDR0 0xa040
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#define STATION_ADDR1 0xa044
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#define RGMII_REG_0 0x27e0
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#define ICM_CONFIG0_REG_0 0x2c00
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#define ICM_CONFIG2_REG_0 0x2c08
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#define ECM_CONFIG0_REG_0 0x2d00
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/* Register fields */
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#define SOFT_RESET BIT(31)
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#define TX_EN BIT(0)
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#define RX_EN BIT(2)
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#define PAD_CRC BIT(2)
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#define CRC_EN BIT(1)
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#define FULL_DUPLEX BIT(0)
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#define INTF_MODE_POS 8
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#define INTF_MODE_LEN 2
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#define HD_MODE_POS 25
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#define HD_MODE_LEN 2
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#define CFG_MACMODE_POS 18
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#define CFG_MACMODE_LEN 2
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#define CFG_WAITASYNCRD_POS 0
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#define CFG_WAITASYNCRD_LEN 16
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#define CFG_SPEED_125_POS 24
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#define CFG_WFIFOFULLTHR_POS 0
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#define CFG_WFIFOFULLTHR_LEN 7
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#define MGMT_CLOCK_SEL_POS 0
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#define MGMT_CLOCK_SEL_LEN 3
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#define PHY_ADDR_POS 8
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#define PHY_ADDR_LEN 5
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#define REG_ADDR_POS 0
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#define REG_ADDR_LEN 5
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#define MII_MGMT_BUSY BIT(0)
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#define MII_READ_CYCLE BIT(0)
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#define CFG_WAITASYNCRD_EN BIT(16)
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static inline void xgene_set_reg_bits(u32 *var, int pos, int len, u32 val)
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{
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u32 mask = GENMASK(pos + len, pos);
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*var &= ~mask;
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*var |= ((val << pos) & mask);
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}
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static inline u32 xgene_get_reg_bits(u32 var, int pos, int len)
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{
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u32 mask = GENMASK(pos + len, pos);
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return (var & mask) >> pos;
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}
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#define SET_REG_BITS(var, field, val) \
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xgene_set_reg_bits(var, field ## _POS, field ## _LEN, val)
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#define SET_REG_BIT(var, field, val) \
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xgene_set_reg_bits(var, field ## _POS, 1, val)
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#define GET_REG_BITS(var, field) \
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xgene_get_reg_bits(var, field ## _POS, field ## _LEN)
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#define GET_REG_BIT(var, field) ((var) & (field))
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struct xge_pdata;
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void xge_mac_reset(struct xge_pdata *pdata);
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void xge_mac_set_speed(struct xge_pdata *pdata);
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void xge_mac_enable(struct xge_pdata *pdata);
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void xge_mac_disable(struct xge_pdata *pdata);
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void xge_mac_init(struct xge_pdata *pdata);
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void xge_mac_set_station_addr(struct xge_pdata *pdata);
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#endif /* __XGENE_ENET_V2_MAC_H__ */
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