threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
50 lines
1.6 KiB
C
50 lines
1.6 KiB
C
/*
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* Intel MIC Platform Software Stack (MPSS)
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*
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* Copyright(c) 2013 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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* Disclaimer: The codes contained in these modules may be specific to
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* the Intel Software Development Platform codenamed: Knights Ferry, and
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* the Intel product codenamed: Knights Corner, and are not backward
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* compatible with other Intel products. Additionally, Intel will NOT
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* support the codes or instruction set in future products.
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*
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* Intel MIC Card driver.
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*
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*/
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#ifndef _MIC_X100_CARD_H_
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#define _MIC_X100_CARD_H_
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#define MIC_X100_MMIO_BASE 0x08007C0000ULL
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#define MIC_X100_MMIO_LEN 0x00020000ULL
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#define MIC_X100_SBOX_BASE_ADDRESS 0x00010000ULL
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#define MIC_X100_SBOX_SPAD0 0x0000AB20
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#define MIC_X100_SBOX_SDBIC0 0x0000CC90
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#define MIC_X100_SBOX_SDBIC0_DBREQ_BIT 0x80000000
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#define MIC_X100_SBOX_RDMASR0 0x0000B180
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#define MIC_X100_SBOX_APICICR0 0x0000A9D0
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#define MIC_X100_MAX_DOORBELL_IDX 8
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#define MIC_X100_NUM_SBOX_IRQ 8
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#define MIC_X100_NUM_RDMASR_IRQ 8
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#define MIC_X100_SBOX_IRQ_BASE 0
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#define MIC_X100_RDMASR_IRQ_BASE 17
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#define MIC_X100_IRQ_BASE 26
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#endif
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