threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
100 lines
2.3 KiB
C
100 lines
2.3 KiB
C
/*
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* Copyright (C) 2017 MediaTek Inc.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __SCP_DVFS_H__
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#define __SCP_DVFS_H__
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#define PLL_ENABLE (1)
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#define PLL_DISABLE (0)
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#define DVFS_STATUS_OK (0)
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#define DVFS_STATUS_BUSY (-1)
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#define DVFS_REQUEST_SAME_CLOCK (-2)
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#define DVFS_STATUS_ERR (-3)
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#define DVFS_STATUS_TIMEOUT (-4)
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#define DVFS_CLK_ERROR (-5)
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#define DVFS_STATUS_CMD_FIX (-6)
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#define DVFS_STATUS_CMD_LIMITED (-7)
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#define DVFS_STATUS_CMD_DISABLE (-8)
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enum scp_state_enum {
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IN_DEBUG_IDLE = 1,
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ENTERING_SLEEP = 2,
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IN_SLEEP = 4,
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ENTERING_ACTIVE = 8,
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IN_ACTIVE = 16,
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};
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enum {
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CLK_SYS_EN_BIT = 0,
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CLK_HIGH_EN_BIT = 1,
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CLK_HIGH_CG_BIT = 2,
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CLK_SYS_IRQ_EN_BIT = 16,
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CLK_HIGH_IRQ_EN_BIT = 17,
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};
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/*#ifdef CONFIG_PINCTRL_MT6797*/
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enum clk_opp_enum {
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CLK_26M = 26,
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CLK_OPP0 = 250,
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CLK_OPP1 = 273,
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CLK_OPP2 = 330,
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CLK_OPP3 = 416,
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CLK_INVALID_OPP,
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};
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enum clk_div_enum {
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CLK_DIV_1 = 0,
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CLK_DIV_2 = 1,
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CLK_DIV_4 = 2,
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CLK_DIV_8 = 3,
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CLK_DIV_UNKNOWN,
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};
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enum voltage_enum {
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SPM_VOLTAGE_800_D = 0,
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SPM_VOLTAGE_800,
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SPM_VOLTAGE_900,
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SPM_VOLTAGE_1000,
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SPM_VOLTAGE_TYPE_NUM,
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};
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struct mt_scp_pll_t {
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struct clk *clk_mux;
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struct clk *clk_pll0;
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struct clk *clk_pll1;
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struct clk *clk_pll2;
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struct clk *clk_pll3;
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struct clk *clk_pll4;
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struct clk *clk_pll5;
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struct clk *clk_pll6;
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struct clk *clk_pll7;
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};
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extern int scp_pll_ctrl_set(unsigned int pll_ctrl_flag, unsigned int pll_sel);
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extern int scp_set_pmic_vcore(unsigned int cur_freq);
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extern unsigned int scp_get_dvfs_opp(void);
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extern uint32_t scp_get_freq(void);
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extern int scp_request_freq(void);
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extern void scp_pll_mux_set(unsigned int pll_ctrl_flag);
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extern void wait_scp_dvfs_init_done(void);
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extern int __init scp_dvfs_init(void);
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extern void __exit scp_dvfs_exit(void);
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/* scp dvfs variable*/
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extern unsigned int scp_expected_freq;
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extern unsigned int scp_current_freq;
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extern spinlock_t scp_awake_spinlock;
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#endif /* __SCP_DVFS_H__ */
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