threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
129 lines
2.8 KiB
C
129 lines
2.8 KiB
C
/******************************************************************************
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* mtk_pwm.h PWM Drvier
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*
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* Copyright (c) 2016, Media Teck.inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public Licence,
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* version 2, as publish by the Free Software Foundation.
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*
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* This program is distributed and in hope it will be useful, but WITHOUT
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* ANY WARRNTY; without even the implied warranty of MERCHANTABITLITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*
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*/
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#ifndef __MT_PWM_H__
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#define __MT_PWM_H__
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#include <linux/types.h>
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#include <mach/mtk_pwm_hal.h>
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struct pwm_easy_config {
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u32 pwm_no;
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u32 duty;
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u32 clk_src;
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u32 clk_div;
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u16 duration;
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u8 pmic_pad;
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};
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struct pwm_spec_config {
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u32 pwm_no;
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u32 mode;
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u32 clk_div;
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u32 clk_src;
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u8 intr;
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u8 pmic_pad;
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union {
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/* for old mode */
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struct _PWM_OLDMODE_REGS {
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u16 IDLE_VALUE;
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u16 GUARD_VALUE;
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u16 GDURATION;
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u16 WAVE_NUM;
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u16 DATA_WIDTH;
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u16 THRESH;
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} PWM_MODE_OLD_REGS;
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/* for fifo mode */
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struct _PWM_MODE_FIFO_REGS {
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u32 IDLE_VALUE;
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u32 GUARD_VALUE;
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u32 STOP_BITPOS_VALUE;
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u16 HDURATION;
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u16 LDURATION;
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u32 GDURATION;
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u32 SEND_DATA0;
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u32 SEND_DATA1;
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u32 WAVE_NUM;
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} PWM_MODE_FIFO_REGS;
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/* for memory mode */
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struct _PWM_MODE_MEMORY_REGS {
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u32 IDLE_VALUE;
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u32 GUARD_VALUE;
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u32 STOP_BITPOS_VALUE;
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u16 HDURATION;
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u16 LDURATION;
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u16 GDURATION;
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dma_addr_t BUF0_BASE_ADDR;
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u32 BUF0_SIZE;
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u16 WAVE_NUM;
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} PWM_MODE_MEMORY_REGS;
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/* for RANDOM mode */
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struct _PWM_MODE_RANDOM_REGS {
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u16 IDLE_VALUE;
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u16 GUARD_VALUE;
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u32 STOP_BITPOS_VALUE;
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u16 HDURATION;
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u16 LDURATION;
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u16 GDURATION;
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dma_addr_t BUF0_BASE_ADDR;
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u32 BUF0_SIZE;
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dma_addr_t BUF1_BASE_ADDR;
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u32 BUF1_SIZE;
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u16 WAVE_NUM;
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u32 VALID;
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} PWM_MODE_RANDOM_REGS;
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/* for seq mode */
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struct _PWM_MODE_DELAY_REGS {
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/* u32 ENABLE_DELAY_VALUE; */
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u16 PWM3_DELAY_DUR;
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u32 PWM3_DELAY_CLK;
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/* 0: block clock source, 1: block/1625 clock source */
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u16 PWM4_DELAY_DUR;
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u32 PWM4_DELAY_CLK;
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u16 PWM5_DELAY_DUR;
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u32 PWM5_DELAY_CLK;
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} PWM_MODE_DELAY_REGS;
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};
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};
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s32 pwm_set_easy_config(struct pwm_easy_config *conf);
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s32 pwm_set_spec_config(struct pwm_spec_config *conf);
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void mt_pwm_dump_regs(void);
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void mt_pwm_disable(u32 pwm_no, u8 pmic_pad);
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/*----------3dLCM support-----------*/
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void mt_set_pwm_3dlcm_enable(u8 enable);
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/*
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* set "pwm_no" inversion of pwm base or not
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*/
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void mt_set_pwm_3dlcm_inv(u32 pwm_no, u8 inv);
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/* void mt_set_pwm_3dlcm_base(u32 pwm_no); */
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/* void mt_pwm_26M_clk_enable(u32 enable); */
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s32 mt_set_intr_ack(u32 pwm_intr_ack_bit);
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s32 mt_set_intr_enable(u32 pwm_intr_enable_bit);
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s32 mt_get_intr_status(u32 pwm_intr_status_bit);
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#endif
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