threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
253 lines
6.3 KiB
C
253 lines
6.3 KiB
C
/*
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* Copyright (C) 2013-2016, Shenzhen Huiding Technology Co., Ltd.
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* Copyright (C) 2021 XiaoMi, Inc.
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* All Rights Reserved.
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*/
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#ifndef __GF_SPI_TEE_H
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#define __GF_SPI_TEE_H
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#include <linux/types.h>
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#include <linux/netlink.h>
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#include <linux/cdev.h>
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#include <linux/input.h>
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#ifndef CONFIG_SPI_MT65XX
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#include "mtk_spi.h"
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#endif
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#ifdef CONFIG_HAS_EARLYSUSPEND
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#include <linux/earlysuspend.h>
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#else
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#include <linux/notifier.h>
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#endif
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/**************************debug******************************/
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#define ERR_LOG (0)
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#define INFO_LOG (1)
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#define DEBUG_LOG (2)
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/* debug log setting */
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u8 g_debug_level = DEBUG_LOG;
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#define gf_debug(level, fmt, args...) do { \
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if (g_debug_level >= level) {\
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pr_warn("[gf] " fmt, ##args); \
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} \
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} while (0)
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#define FUNC_ENTRY() gf_debug(DEBUG_LOG, "%s, %d, enter\n", __func__, __LINE__)
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#define FUNC_EXIT() gf_debug(DEBUG_LOG, "%s, %d, exit\n", __func__, __LINE__)
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/**********************IO Magic**********************/
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#define GF_IOC_MAGIC 'g'
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#define GF_NAV_INPUT_UP KEY_UP
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#define GF_NAV_INPUT_DOWN KEY_DOWN
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#define GF_NAV_INPUT_LEFT KEY_LEFT
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#define GF_NAV_INPUT_RIGHT KEY_RIGHT
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#define GF_NAV_INPUT_CLICK KEY_VOLUMEDOWN
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#define GF_NAV_INPUT_DOUBLE_CLICK KEY_VOLUMEUP
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#define GF_NAV_INPUT_LONG_PRESS KEY_SEARCH
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#define GF_NAV_INPUT_HEAVY KEY_CHAT
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typedef enum gf_nav_event {
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GF_NAV_NONE = 0,
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GF_NAV_FINGER_UP,
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GF_NAV_FINGER_DOWN,
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GF_NAV_UP,
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GF_NAV_DOWN,
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GF_NAV_LEFT,
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GF_NAV_RIGHT,
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GF_NAV_CLICK,
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GF_NAV_HEAVY,
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GF_NAV_LONG_PRESS,
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GF_NAV_DOUBLE_CLICK,
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} gf_nav_event_t;
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typedef enum gf_key_event {
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GF_KEY_NONE = 0,
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GF_KEY_POWER,
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GF_KEY_MENU,
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GF_KEY_BACK,
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GF_KEY_CAMERA,
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GF_KEY_HOME_DOUBLE_CLICK,
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} gf_key_event_t;
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enum gf_netlink_cmd {
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GF_NETLINK_TEST = 0,
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GF_NETLINK_IRQ = 1,
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GF_NETLINK_SCREEN_OFF,
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GF_NETLINK_SCREEN_ON
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};
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struct gf_ioc_transfer {
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u8 cmd; /* spi read = 0, spi write = 1 */
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u8 reserved;
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u16 addr;
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u32 len;
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u8 *buf;
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};
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struct gf_ioc_transfer_raw {
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u32 len;
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u8 *read_buf;
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u8 *write_buf;
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uint32_t high_time;
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uint32_t low_time;
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};
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struct gf_ioc_chip_info {
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u8 vendor_id;
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u8 mode;
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u8 operation;
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u8 reserved[5];
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};
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/* define for gf_spi_cfg_t->speed_hz */
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#define GF_SPI_SPEED_LOW 1
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#define GF_SPI_SPEED_MEDIUM 6
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#define GF_SPI_SPEED_HIGH 9
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enum gf_spi_cpol {
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GF_SPI_CPOL_0,
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GF_SPI_CPOL_1
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};
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enum gf_spi_cpha {
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GF_SPI_CPHA_0,
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GF_SPI_CPHA_1
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};
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typedef struct {
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unsigned int cs_setuptime;
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unsigned int cs_holdtime;
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unsigned int cs_idletime;
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unsigned int speed_hz; //spi clock rate
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unsigned int duty_cycle; //The time ratio of active level in a period. Default value is 50. that means high time and low time is same.
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enum gf_spi_cpol cpol;
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enum gf_spi_cpol cpha;
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} gf_spi_cfg_t;
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/* define commands */
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#define GF_IOC_INIT _IOR(GF_IOC_MAGIC, 0, u8)
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#define GF_IOC_EXIT _IO(GF_IOC_MAGIC, 1)
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#define GF_IOC_RESET _IO(GF_IOC_MAGIC, 2)
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#define GF_IOC_ENABLE_IRQ _IO(GF_IOC_MAGIC, 3)
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#define GF_IOC_DISABLE_IRQ _IO(GF_IOC_MAGIC, 4)
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#define GF_IOC_ENABLE_SPI_CLK _IOW(GF_IOC_MAGIC, 5, uint32_t)
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#define GF_IOC_DISABLE_SPI_CLK _IO(GF_IOC_MAGIC, 6)
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#define GF_IOC_ENABLE_POWER _IO(GF_IOC_MAGIC, 7)
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#define GF_IOC_DISABLE_POWER _IO(GF_IOC_MAGIC, 8)
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/* fp sensor has change to sleep mode while screen off */
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#define GF_IOC_ENTER_SLEEP_MODE _IO(GF_IOC_MAGIC, 10)
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#define GF_IOC_GET_FW_INFO _IOR(GF_IOC_MAGIC, 11, u8)
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#define GF_IOC_REMOVE _IO(GF_IOC_MAGIC, 12)
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#define GF_IOC_CHIP_INFO _IOW(GF_IOC_MAGIC, 13, struct gf_ioc_chip_info)
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#define GF_IOC_NAV_EVENT _IOW(GF_IOC_MAGIC, 14, gf_nav_event_t)
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/* for SPI REE transfer */
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#define GF_IOC_TRANSFER_CMD _IOWR(GF_IOC_MAGIC, 15, struct gf_ioc_transfer)
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#define GF_IOC_TRANSFER_RAW_CMD _IOWR(GF_IOC_MAGIC, 16, struct gf_ioc_transfer_raw)
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#define GF_IOC_SPI_INIT_CFG_CMD _IOW(GF_IOC_MAGIC, 17, gf_spi_cfg_t)
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#define GF_IOC_MAXNR 18 /* THIS MACRO IS NOT USED NOW... */
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struct gf_device {
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dev_t devno;
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struct cdev cdev;
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struct device *device;
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struct class *class;
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struct spi_device *spi;
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struct platform_device *pldev;
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int device_count;
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#ifndef CONFIG_SPI_MT65XX
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struct mt_chip_conf spi_mcc;
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#endif
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spinlock_t spi_lock;
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struct list_head device_entry;
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struct input_dev *input;
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u8 *spi_buffer; /* only used for SPI transfer internal */
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struct mutex buf_lock;
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struct mutex release_lock;
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u8 buf_status;
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/* for netlink use */
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struct sock *nl_sk;
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#ifdef CONFIG_HAS_EARLYSUSPEND
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struct early_suspend early_suspend;
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#else
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struct notifier_block notifier;
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#endif
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u8 probe_finish;
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u8 irq_count;
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/* bit24-bit32 of signal count */
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/* bit16-bit23 of event type, 1: key down; 2: key up; 3: fp data ready; 4: home key */
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/* bit0-bit15 of event type, buffer status register */
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u32 event_type;
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u8 sig_count;
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u8 is_sleep_mode;
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u8 system_status;
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u32 cs_gpio;
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u32 reset_gpio;
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u32 irq_gpio;
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u32 irq_num;
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u8 need_update;
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u32 irq;
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u8 fb_black;
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u8 wait_finger_down;
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#ifdef CONFIG_OF
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struct pinctrl *pinctrl_gpios;
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struct pinctrl_state *pins_irq;
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struct pinctrl_state *pins_miso_spi, *pins_miso_pullhigh, *pins_miso_pulllow;
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struct pinctrl_state *pins_reset_high, *pins_reset_low;
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#endif
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};
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/**************************REE SPI******************************/
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#ifndef SUPPORT_REE_SPI
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#define SUPPORT_REE_SPI
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//#define SUPPORT_REE_OSWEGO
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#endif
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#ifdef SUPPORT_REE_SPI
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#define HIGH_SPEED 6
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#define LOW_SPEED 1
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#define ERR_NO_SENSOR 111
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#define ERR_FW_DESTROY 112
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#define ERR_PREPARE_FAIL 113
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/**********************function defination**********************/
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#ifndef CONFIG_SPI_MT65XX
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void gf_spi_setup_conf_ree(struct gf_device *gf_dev, u32 speed, enum spi_transfer_mode mode);
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#endif
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int gf_spi_read_bytes_ree(struct gf_device *gf_dev, u16 addr, u32 data_len, u8 *rx_buf);
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int gf_spi_write_bytes_ree(struct gf_device *gf_dev, u16 addr, u32 data_len, u8 *tx_buf);
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int gf_spi_read_byte_ree(struct gf_device *gf_dev, u16 addr, u8 *value);
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int gf_spi_write_byte_ree(struct gf_device *gf_dev, u16 addr, u8 value);
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int gf_ioctl_transfer_raw_cmd(struct gf_device *gf_dev, unsigned long arg,unsigned int bufsiz);
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#ifndef CONFIG_SPI_MT65XX
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int gf_ioctl_spi_init_cfg_cmd(struct mt_chip_conf *mcc, unsigned long arg);
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#endif
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#ifdef CONFIG_SPI_MT65XX
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extern void mt_spi_enable_master_clk(struct spi_device *spidev);
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extern void mt_spi_disable_master_clk(struct spi_device *spidev);
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#endif
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#endif
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#endif /* __GF_SPI_TEE_H */
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