threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
40 lines
879 B
C
40 lines
879 B
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* NSC/Cyrix CPU indexed register access. Must be inlined instead of
|
|
* macros to ensure correct access ordering
|
|
* Access order is always 0x22 (=offset), 0x23 (=value)
|
|
*
|
|
* When using the old macros a line like
|
|
* setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
|
|
* gets expanded to:
|
|
* do {
|
|
* outb((CX86_CCR2), 0x22);
|
|
* outb((({
|
|
* outb((CX86_CCR2), 0x22);
|
|
* inb(0x23);
|
|
* }) | 0x88), 0x23);
|
|
* } while (0);
|
|
*
|
|
* which in fact violates the access order (= 0x22, 0x22, 0x23, 0x23).
|
|
*/
|
|
|
|
static inline u8 getCx86(u8 reg)
|
|
{
|
|
outb(reg, 0x22);
|
|
return inb(0x23);
|
|
}
|
|
|
|
static inline void setCx86(u8 reg, u8 data)
|
|
{
|
|
outb(reg, 0x22);
|
|
outb(data, 0x23);
|
|
}
|
|
|
|
#define getCx86_old(reg) ({ outb((reg), 0x22); inb(0x23); })
|
|
|
|
#define setCx86_old(reg, data) do { \
|
|
outb((reg), 0x22); \
|
|
outb((data), 0x23); \
|
|
} while (0)
|
|
|