threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
55 lines
1.3 KiB
C
55 lines
1.3 KiB
C
#ifndef __ASM_SH_SH7763RDP_H
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#define __ASM_SH_SH7763RDP_H
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/*
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* linux/include/asm-sh/sh7763drp.h
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*
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* Copyright (C) 2008 Renesas Solutions
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* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <asm/addrspace.h>
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/* clock control */
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#define MSTPCR1 0xFFC80038
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/* PORT */
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#define PORT_PSEL0 0xFFEF0070
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#define PORT_PSEL1 0xFFEF0072
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#define PORT_PSEL2 0xFFEF0074
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#define PORT_PSEL3 0xFFEF0076
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#define PORT_PSEL4 0xFFEF0078
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#define PORT_PACR 0xFFEF0000
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#define PORT_PCCR 0xFFEF0004
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#define PORT_PFCR 0xFFEF000A
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#define PORT_PGCR 0xFFEF000C
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#define PORT_PHCR 0xFFEF000E
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#define PORT_PICR 0xFFEF0010
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#define PORT_PJCR 0xFFEF0012
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#define PORT_PKCR 0xFFEF0014
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#define PORT_PLCR 0xFFEF0016
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#define PORT_PMCR 0xFFEF0018
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#define PORT_PNCR 0xFFEF001A
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/* FPGA */
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#define CPLD_BOARD_ID_ERV_REG 0xB1000000
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#define CPLD_CPLD_CMD_REG 0xB1000006
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/*
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* USB SH7763RDP board can use Host only.
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*/
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#define USB_USBHSC 0xFFEC80f0
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/* arch/sh/boards/renesas/sh7763rdp/irq.c */
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void init_sh7763rdp_IRQ(void);
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int sh7763rdp_irq_demux(int irq);
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#define __IO_PREFIX sh7763rdp
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#include <asm/io_generic.h>
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#endif /* __ASM_SH_SH7763RDP_H */
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