threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
60 lines
1.4 KiB
C
60 lines
1.4 KiB
C
/*
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* Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#ifndef _ASM_NIOS2_CPUINFO_H
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#define _ASM_NIOS2_CPUINFO_H
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#include <linux/types.h>
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struct cpuinfo {
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/* Core CPU configuration */
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char cpu_impl[12];
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u32 cpu_clock_freq;
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bool mmu;
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bool has_div;
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bool has_mul;
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bool has_mulx;
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bool has_bmx;
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bool has_cdx;
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/* CPU caches */
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u32 icache_line_size;
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u32 icache_size;
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u32 dcache_line_size;
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u32 dcache_size;
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/* TLB */
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u32 tlb_pid_num_bits; /* number of bits used for the PID in TLBMISC */
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u32 tlb_num_ways;
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u32 tlb_num_ways_log2;
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u32 tlb_num_entries;
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u32 tlb_num_lines;
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u32 tlb_ptr_sz;
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/* Addresses */
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u32 reset_addr;
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u32 exception_addr;
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u32 fast_tlb_miss_exc_addr;
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};
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extern struct cpuinfo cpuinfo;
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extern void setup_cpuinfo(void);
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#endif /* _ASM_NIOS2_CPUINFO_H */
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