threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
37 lines
1.1 KiB
C
37 lines
1.1 KiB
C
/*
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* Copyright (C) 2004 Microtronix Datacom Ltd.
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for more
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* details.
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*/
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#ifndef _ASM_NIOS2_CACHE_H
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#define _ASM_NIOS2_CACHE_H
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#define NIOS2_DCACHE_SIZE CONFIG_NIOS2_DCACHE_SIZE
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#define NIOS2_ICACHE_SIZE CONFIG_NIOS2_ICACHE_SIZE
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#define NIOS2_DCACHE_LINE_SIZE CONFIG_NIOS2_DCACHE_LINE_SIZE
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#define NIOS2_ICACHE_LINE_SHIFT 5
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#define NIOS2_ICACHE_LINE_SIZE (1 << NIOS2_ICACHE_LINE_SHIFT)
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/* bytes per L1 cache line */
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#define L1_CACHE_SHIFT NIOS2_ICACHE_LINE_SHIFT
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#define L1_CACHE_BYTES NIOS2_ICACHE_LINE_SIZE
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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#define __cacheline_aligned
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#define ____cacheline_aligned
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#endif
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