threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
156 lines
3.2 KiB
C
156 lines
3.2 KiB
C
/* timex.h: MN2WS0038 architecture timer specifications
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*
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* Copyright (C) 2002, 2010 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_UNIT_TIMEX_H
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#define _ASM_UNIT_TIMEX_H
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#include <asm/timer-regs.h>
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#include <unit/clock.h>
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#include <asm/param.h>
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/*
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* jiffies counter specifications
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*/
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#define TMJCBR_MAX 0xffffff /* 24bit */
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#define TMJCIRQ TMTIRQ
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#ifndef __ASSEMBLY__
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#define MN10300_SRC_IOBCLK MN10300_IOBCLK
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#ifndef HZ
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# error HZ undeclared.
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#endif /* !HZ */
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#define MN10300_JCCLK (MN10300_SRC_IOBCLK)
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#define MN10300_TSCCLK (MN10300_SRC_IOBCLK)
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#define MN10300_JC_PER_HZ ((MN10300_JCCLK + HZ / 2) / HZ)
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#define MN10300_TSC_PER_HZ ((MN10300_TSCCLK + HZ / 2) / HZ)
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/* Check bit width of MTM interval value that sets base register */
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#if (MN10300_JC_PER_HZ - 1) > TMJCBR_MAX
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# error MTM tick timer interval value is overflow.
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#endif
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static inline void stop_jiffies_counter(void)
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{
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u16 tmp;
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TMTMD = 0;
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tmp = TMTMD;
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}
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static inline void reload_jiffies_counter(u32 cnt)
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{
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u32 tmp;
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TMTBR = cnt;
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tmp = TMTBR;
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TMTMD = TMTMD_TMTLDE;
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TMTMD = TMTMD_TMTCNE;
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tmp = TMTMD;
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}
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#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS) && \
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!defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
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/*
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* If we aren't using broadcasting, each core needs its own event timer.
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* Since CPU0 uses the tick timer which is 24-bits, we use timer 4 & 5
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* cascaded to 32-bits for CPU1 (but only really use 24-bits to match
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* CPU0).
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*/
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#define TMJC1IRQ TM5IRQ
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static inline void stop_jiffies_counter1(void)
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{
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u8 tmp;
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TM4MD = 0;
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TM5MD = 0;
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tmp = TM4MD;
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tmp = TM5MD;
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}
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static inline void reload_jiffies_counter1(u32 cnt)
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{
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u32 tmp;
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TM45BR = cnt;
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tmp = TM45BR;
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TM4MD = TM4MD_INIT_COUNTER;
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tmp = TM4MD;
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TM5MD = TM5MD_SRC_TM4CASCADE | TM5MD_INIT_COUNTER;
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TM5MD = TM5MD_SRC_TM4CASCADE | TM5MD_COUNT_ENABLE;
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tmp = TM5MD;
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TM4MD = TM4MD_COUNT_ENABLE;
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tmp = TM4MD;
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}
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#endif /* CONFIG_SMP&GENERIC_CLOCKEVENTS&!GENERIC_CLOCKEVENTS_BROADCAST */
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#endif /* !__ASSEMBLY__ */
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/*
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* timestamp counter specifications
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*/
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#define TMTSCBR_MAX 0xffffffff
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#ifndef __ASSEMBLY__
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/* Use 32-bit timestamp counter */
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#define TMTSCMD TMSMD
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#define TMTSCBR TMSBR
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#define TMTSCBC TMSBC
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#define TMTSCICR TMSICR
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static inline void startup_timestamp_counter(void)
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{
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u32 sync;
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/* set up TMS(Timestamp) 32bit timer register to count real time
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* - count down from 4Gig-1 to 0 and wrap at IOBCLK rate
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*/
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TMTSCBR = TMTSCBR_MAX;
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sync = TMTSCBR;
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TMTSCICR = 0;
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sync = TMTSCICR;
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TMTSCMD = TMTMD_TMTLDE;
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TMTSCMD = TMTMD_TMTCNE;
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sync = TMTSCMD;
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}
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static inline void shutdown_timestamp_counter(void)
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{
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TMTSCMD = 0;
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}
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/*
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* we use a cascaded pair of 16-bit down-counting timers to count I/O
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* clock cycles for the purposes of time keeping
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*/
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typedef unsigned long cycles_t;
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static inline cycles_t read_timestamp_counter(void)
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{
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return (cycles_t)~TMTSCBC;
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_UNIT_TIMEX_H */
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