threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
73 lines
1.7 KiB
C
73 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Static Memory Controller
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/syscore_ops.h>
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#include <mach/hardware.h>
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#include <mach/smemc.h>
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#ifdef CONFIG_PM
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static unsigned long msc[2];
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static unsigned long sxcnfg, memclkcfg;
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static unsigned long csadrcfg[4];
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static int pxa3xx_smemc_suspend(void)
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{
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msc[0] = __raw_readl(MSC0);
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msc[1] = __raw_readl(MSC1);
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sxcnfg = __raw_readl(SXCNFG);
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memclkcfg = __raw_readl(MEMCLKCFG);
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csadrcfg[0] = __raw_readl(CSADRCFG0);
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csadrcfg[1] = __raw_readl(CSADRCFG1);
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csadrcfg[2] = __raw_readl(CSADRCFG2);
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csadrcfg[3] = __raw_readl(CSADRCFG3);
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return 0;
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}
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static void pxa3xx_smemc_resume(void)
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{
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__raw_writel(msc[0], MSC0);
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__raw_writel(msc[1], MSC1);
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__raw_writel(sxcnfg, SXCNFG);
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__raw_writel(memclkcfg, MEMCLKCFG);
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__raw_writel(csadrcfg[0], CSADRCFG0);
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__raw_writel(csadrcfg[1], CSADRCFG1);
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__raw_writel(csadrcfg[2], CSADRCFG2);
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__raw_writel(csadrcfg[3], CSADRCFG3);
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/* CSMSADRCFG wakes up in its default state (0), so we need to set it */
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__raw_writel(0x2, CSMSADRCFG);
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}
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static struct syscore_ops smemc_syscore_ops = {
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.suspend = pxa3xx_smemc_suspend,
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.resume = pxa3xx_smemc_resume,
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};
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static int __init smemc_init(void)
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{
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if (cpu_is_pxa3xx()) {
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/*
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* The only documentation we have on the
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* Chip Select Configuration Register (CSMSADRCFG) is that
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* it must be programmed to 0x2.
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* Moreover, in the bit definitions, the second bit
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* (CSMSADRCFG[1]) is called "SETALWAYS".
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* Other bits are reserved in this register.
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*/
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__raw_writel(0x2, CSMSADRCFG);
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register_syscore_ops(&smemc_syscore_ops);
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}
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return 0;
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}
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subsys_initcall(smemc_init);
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#endif
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