threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
25 lines
660 B
Plaintext
25 lines
660 B
Plaintext
NVIDIA Tegra20 timer
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The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
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running counter. The first two channels may also trigger a watchdog reset.
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Required properties:
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- compatible : should be "nvidia,tegra20-timer".
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- reg : Specifies base physical address and size of the registers.
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- interrupts : A list of 4 interrupts; one per timer channel.
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- clocks : Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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Example:
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timer {
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compatible = "nvidia,tegra20-timer";
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reg = <0x60005000 0x60>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04>;
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clocks = <&tegra_car 132>;
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};
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