threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
29 lines
997 B
Plaintext
29 lines
997 B
Plaintext
* Renesas R-Car PWM Timer Controller
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Required Properties:
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- compatible: should be "renesas,pwm-rcar" and one of the following.
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- "renesas,pwm-r8a7778": for R-Car M1A
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- "renesas,pwm-r8a7779": for R-Car H1
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- "renesas,pwm-r8a7790": for R-Car H2
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- "renesas,pwm-r8a7791": for R-Car M2-W
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- "renesas,pwm-r8a7794": for R-Car E2
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- "renesas,pwm-r8a7795": for R-Car H3
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- "renesas,pwm-r8a7796": for R-Car M3-W
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- reg: base address and length of the registers block for the PWM.
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- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
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the cells format.
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- clocks: clock phandle and specifier pair.
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- pinctrl-0: phandle, referring to a default pin configuration node.
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- pinctrl-names: Set to "default".
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Example: R8A7790 (R-Car H2) PWM Timer node
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pwm0: pwm@e6e30000 {
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compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
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reg = <0 0xe6e30000 0 0x8>;
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#pwm-cells = <2>;
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clocks = <&mstp5_clks R8A7790_CLK_PWM>;
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pinctrl-0 = <&pwm0_pins>;
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pinctrl-names = "default";
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};
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