threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
68 lines
2.3 KiB
Plaintext
68 lines
2.3 KiB
Plaintext
MIPS Global Interrupt Controller (GIC)
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The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
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It also supports local (per-processor) interrupts and software-generated
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interrupts which can be used as IPIs. The GIC also includes a free-running
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global timer, per-CPU count/compare timers, and a watchdog.
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Required properties:
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- compatible : Should be "mti,gic".
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt specifier. Should be 3.
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- The first cell is the type of interrupt, local or shared.
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See <include/dt-bindings/interrupt-controller/mips-gic.h>.
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- The second cell is the GIC interrupt number.
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- The third cell encodes the interrupt flags.
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See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
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flags.
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Optional properties:
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- reg : Base address and length of the GIC registers. If not present,
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the base address reported by the hardware GCR_GIC_BASE will be used.
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- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
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to which the GIC may not route interrupts. Valid values are 2 - 7.
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This property is ignored if the CPU is started in EIC mode.
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- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
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reserved for IPIs.
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It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
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of the reserved range.
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If not specified, the driver will allocate the last 2 * number of VPEs in the
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system.
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Required properties for timer sub-node:
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- compatible : Should be "mti,gic-timer".
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- interrupts : Interrupt for the GIC local timer.
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Optional properties for timer sub-node:
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- clocks : GIC timer operating clock.
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- clock-frequency : Clock frequency at which the GIC timers operate.
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Note that one of clocks or clock-frequency must be specified.
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Example:
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gic: interrupt-controller@1bdc0000 {
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compatible = "mti,gic";
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reg = <0x1bdc0000 0x20000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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mti,reserved-cpu-vectors = <7>;
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mti,reserved-ipi-vectors = <40 8>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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clock-frequency = <50000000>;
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};
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};
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uart@18101400 {
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...
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
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...
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};
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