threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
56 lines
2.1 KiB
Plaintext
56 lines
2.1 KiB
Plaintext
* NVIDIA Tegra Audio DMA (ADMA) controller
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The Tegra Audio DMA controller that is used for transferring data
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between system memory and the Audio Processing Engine (APE).
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Required properties:
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- compatible: Must be "nvidia,tegra210-adma".
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- reg: Should contain DMA registers location and length. This should be
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a single entry that includes all of the per-channel registers in one
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contiguous bank.
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- interrupt-parent: Phandle to the interrupt parent controller.
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- interrupts: Should contain all of the per-channel DMA interrupts in
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ascending order with respect to the DMA channel index.
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- clocks: Must contain one entry for the ADMA module clock
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(TEGRA210_CLK_D_AUDIO).
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- clock-names: Must contain the name "d_audio" for the corresponding
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'clocks' entry.
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- #dma-cells : Must be 1. The first cell denotes the receive/transmit
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request number and should be between 1 and the maximum number of
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requests supported. This value corresponds to the RX/TX_REQUEST_SELECT
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fields in the ADMA_CHn_CTRL register.
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Example:
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adma: dma@702e2000 {
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compatible = "nvidia,tegra210-adma";
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reg = <0x0 0x702e2000 0x0 0x2000>;
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interrupt-parent = <&tegra_agic>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
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clock-names = "d_audio";
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#dma-cells = <1>;
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};
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