threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
68 lines
4.6 KiB
JSON
68 lines
4.6 KiB
JSON
[
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{
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"EventCode": "0xC7",
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"Counter": "0,1,2,3",
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"UMask": "0x1",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC7",
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"Counter": "0,1,2,3",
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"UMask": "0x2",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC7",
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"Counter": "0,1,2,3",
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"UMask": "0x4",
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"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"EventCode": "0xC7",
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"Counter": "0,1,2,3",
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"UMask": "0x8",
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"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC7",
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"Counter": "0,1,2,3",
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"UMask": "0x10",
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"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC7",
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"Counter": "0,1,2,3",
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"UMask": "0x20",
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"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
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"SampleAfterValue": "2000003",
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"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
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"EventCode": "0xCA",
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"Counter": "0,1,2,3",
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"UMask": "0x1e",
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"EventName": "FP_ASSIST.ANY",
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"SampleAfterValue": "100003",
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"BriefDescription": "Cycles with any input/output SSE or FP assist",
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"CounterMask": "1",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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}
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] |