threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
324 lines
7.9 KiB
C
324 lines
7.9 KiB
C
/*
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* Copyright (C) 2018, SI-IN, Yun Shi (yun.shi@si-in.com).
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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//#define DEBUG
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#define LOG_FLAG "sia8152s_regs"
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#include <linux/regmap.h>
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#include <linux/device.h>
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#include "sia81xx_common.h"
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#include "sia81xx_regmap.h"
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#include "sia8152s_regs.h"
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#define SIA8152S_WRITEABLE_REG_NUM (5)
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static const char sia8152s_palyback_defaults[][SIA8152S_WRITEABLE_REG_NUM] = {
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[SIA81XX_CHANNEL_L] = {
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0x93, //SIA8152_REG_MOD_CFG
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0xE4, //SIA8152_REG_SYS_EN
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0x80, //SIA8152_REG_OVP_CFG
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0x01, //SIA8152_REG_OPC_HCFG
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0x00 //SIA8152_REG_TEST_CFG
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},
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[SIA81XX_CHANNEL_R] = {
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0x93, //SIA8152_REG_MOD_CFG
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0xE4, //SIA8152_REG_SYS_EN
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0x80, //SIA8152_REG_OVP_CFG
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0x01, //SIA8152_REG_OPC_HCFG
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0x00 //SIA8152_REG_TEST_CFG
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}
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};
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static const char sia8152s_voice_defaults[][SIA8152S_WRITEABLE_REG_NUM] = {
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[SIA81XX_CHANNEL_L] = {
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0x63, //SIA8152_REG_MOD_CFG
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0xD4, //SIA8152_REG_SYS_EN
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0x83, //SIA8152_REG_OVP_CFG
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0x01, //SIA8152_REG_OPC_HCFG
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0x00 //SIA8152_REG_TEST_CFG
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},
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[SIA81XX_CHANNEL_R] = {
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0x63, //SIA8152_REG_MOD_CFG
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0xD4, //SIA8152_REG_SYS_EN
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0x83, //SIA8152_REG_OVP_CFG
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0x01, //SIA8152_REG_OPC_HCFG
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0x00 //SIA8152_REG_TEST_CFG
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}
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};
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static const char sia8152s_receiver_defaults[][SIA8152S_WRITEABLE_REG_NUM] = {
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[SIA81XX_CHANNEL_L] = {
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0x43, //SIA8152_REG_MOD_CFG
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0xD4, //SIA8152_REG_SYS_EN
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0x80, //SIA8152_REG_OVP_CFG
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0x01, //SIA8152_REG_OPC_HCFG
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0x00 //SIA8152_REG_TEST_CFG
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},
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[SIA81XX_CHANNEL_R] = {
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0x43, //SIA8152_REG_MOD_CFG
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0xD4, //SIA8152_REG_SYS_EN
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0x80, //SIA8152_REG_OVP_CFG
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0x01, //SIA8152_REG_OPC_HCFG
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0x00 //SIA8152_REG_TEST_CFG
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}
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};
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static const char sia8152s_factory_defaults[][SIA8152S_WRITEABLE_REG_NUM] = {
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[SIA81XX_CHANNEL_L] = {
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0x13, //SIA8152_REG_MOD_CFG
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0xE4, //SIA8152_REG_SYS_EN
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0x80, //SIA8152_REG_OVP_CFG
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0x01, //SIA8152_REG_OPC_HCFG
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0x00 //SIA8152_REG_TEST_CFG
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},
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[SIA81XX_CHANNEL_R] = {
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0x13, //SIA8152_REG_MOD_CFG
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0xE4, //SIA8152_REG_SYS_EN
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0x80, //SIA8152_REG_OVP_CFG
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0x01, //SIA8152_REG_OPC_HCFG
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0x00 //SIA8152_REG_TEST_CFG
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}
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};
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const struct sia81xx_reg_default_val sia8152s_reg_default_val = {
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.chip_type = CHIP_TYPE_SIA8152S,
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.offset = SIA8152S_REG_MOD_CFG,
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.reg_defaults[AUDIO_SCENE_PLAYBACK] = {
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.vals = (char *)sia8152s_palyback_defaults,
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.num = ARRAY_SIZE(sia8152s_palyback_defaults[0])
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},
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.reg_defaults[AUDIO_SCENE_VOICE] = {
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.vals = (char *)sia8152s_voice_defaults,
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.num = ARRAY_SIZE(sia8152s_voice_defaults[0])
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},
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.reg_defaults[AUDIO_SCENE_RECEIVER] = {
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.vals = (char *)sia8152s_receiver_defaults,
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.num = ARRAY_SIZE(sia8152s_receiver_defaults[0])
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},
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.reg_defaults[AUDIO_SCENE_FACTORY] = {
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.vals = (char *)sia8152s_factory_defaults,
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.num = ARRAY_SIZE(sia8152s_factory_defaults[0])
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}
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};
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static const SIA_CHIP_ID_RANGE chip_id_ranges[] = {
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{0x5C, 0x5F}
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};
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static const SIA_REGS trimming_regs[] = {
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{0x09, 0x86},
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{0x10, 0x60},
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{0x13, 0x00}
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};
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static bool sia8152s_writeable_register(
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struct device *dev,
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unsigned int reg)
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{
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switch (reg) {
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case SIA8152S_REG_MOD_CFG ... 0x15: // SIA8152_REG_TEST_CFG :
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return true;
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default :
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break;
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}
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return false;
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}
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static bool sia8152s_readable_register(
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struct device *dev,
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unsigned int reg)
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{
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switch (reg) {
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case SIA8152S_REG_CHIP_ID ... 0x15: // SIA8152_REG_STATE_FLAG2 :
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return true;
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default :
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break;
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}
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return false;
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}
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static bool sia8152s_volatile_register(
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struct device *dev,
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unsigned int reg)
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{
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return true;
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}
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const struct regmap_config sia8152s_regmap_config = {
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.name = "sia8152s",
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.reg_bits = 8,
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.val_bits = 8,
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.reg_stride = 0,
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.pad_bits = 0,
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.cache_type = REGCACHE_NONE,
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.reg_defaults = NULL,
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.num_reg_defaults = 0,
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.writeable_reg = sia8152s_writeable_register,
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.readable_reg = sia8152s_readable_register,
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.volatile_reg = sia8152s_volatile_register,
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.reg_format_endian = REGMAP_ENDIAN_NATIVE,
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.val_format_endian = REGMAP_ENDIAN_NATIVE,
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};
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int sia8152s_check_chip_id(
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struct regmap *regmap)
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{
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int i = 0;
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char val = 0;
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if (0 != sia81xx_regmap_read(regmap, SIA8152S_REG_CHIP_ID, 1, &val))
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return -1;
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for (i = 0; i < ARRAY_SIZE(chip_id_ranges); i++) {
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if (val >= chip_id_ranges[i].begin && val <= chip_id_ranges[i].end)
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return 0;
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}
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return -1;
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}
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static void sia8152s_chip_on(
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struct regmap *regmap, unsigned int scene)
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{
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char val = 0;
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uint8_t ext_regs[SIA8152S_REG_CLD_CFG - SIA8152S_REG_CPADP_CFG + 1]
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= {0x00, 0x00};
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/* for 8152s extra regs */
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sia81xx_regmap_write(regmap,
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SIA8152S_REG_CPADP_CFG, sizeof(ext_regs), (char *)ext_regs);
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if (0 != sia81xx_regmap_read(regmap, SIA8152S_REG_OPC_HCFG, 1, &val))
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return;
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val |= 0x01;
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if (0 != sia81xx_regmap_write(regmap, SIA8152S_REG_OPC_HCFG, 1, &val))
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return;
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/* SIA8152S_REG_OVP_CFG must be set after chip_en */
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val = 0xA0;
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if (0 != sia81xx_regmap_write(regmap, SIA8152S_REG_OVP_CFG, 1, &val))
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return;
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}
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static void sia8152s_chip_off(
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struct regmap *regmap)
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{
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char val = 0;
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if (0 != sia81xx_regmap_write(regmap, SIA8152S_REG_OPC_HCFG, 1, &val))
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return;
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val = 0x10;
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if (0 != sia81xx_regmap_write(regmap, SIA8152S_REG_MOD_CFG, 1, &val))
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return;
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val = 0x80;
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if (0 != sia81xx_regmap_write(regmap, SIA8152S_REG_SYS_EN, 1, &val))
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return;
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mdelay(1); // wait chip power off
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}
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static bool sia8152s_get_chip_en(
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struct regmap *regmap)
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{
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char val = 0;
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if (0 != sia81xx_regmap_read(regmap, SIA8152S_REG_OPC_HCFG, 1, &val))
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return false;
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if (val & 0x01)
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return true;
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return false;
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}
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static void sia8152s_set_pvdd_limit(
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struct regmap *regmap, unsigned int vol)
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{
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char val = 0;
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int8_t cp_ovp = 0;
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if (3200000 > vol || 4800000 < vol) {
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pr_err("[ err][%s] %s: voltage = %u out of range !!! \r\n",
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LOG_FLAG, __func__, vol);
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return;
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}
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cp_ovp = (int8_t)((vol << 3) / 1000000 - 24 - 1);
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if (0 > cp_ovp)
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cp_ovp = 0;
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if (10 < cp_ovp) // pvdd <= 8.5V
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cp_ovp = 10;
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if(0 != sia81xx_regmap_read(regmap, SIA8152S_REG_OVP_CFG, 1, &val))
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return;
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val = (val & 0x0f) | (cp_ovp << 4);
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if(0 != sia81xx_regmap_write(regmap, SIA8152S_REG_OVP_CFG, 1, &val))
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return;
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}
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void sia8152s_check_trimming(
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struct regmap *regmap)
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{
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int i = 0;
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const uint32_t reg_num = ARRAY_SIZE(trimming_regs);
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uint8_t vals[reg_num];
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uint8_t crc = 0;
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/* wait reading trimming data to reg */
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mdelay(1);
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for (i = 0; i < reg_num; i++) {
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if (0 != sia81xx_regmap_read(regmap,
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trimming_regs[i].addr, 1, (char *)&vals[i]))
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return ;
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}
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crc = vals[reg_num - 1];
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if (crc != crc8_maxim(vals, reg_num - 1)) {
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pr_warn("[ warn][%s] %s: trimming failed !! \r\n",
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LOG_FLAG, __func__);
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if (0 != sia81xx_regmap_read(regmap, SIA8152S_REG_OPC_HCFG, 1, (char *)vals))
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return;
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*vals |= 0x02;
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if (0 != sia81xx_regmap_write(regmap, SIA8152S_REG_OPC_HCFG, 1, (char *)vals))
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return;
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for (i = 0; i < reg_num - 1; i++)
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sia81xx_regmap_write(regmap,
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trimming_regs[i].addr, 1, (char *)&(trimming_regs[i].val));
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}
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}
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const struct sia81xx_opt_if sia8152s_opt_if = {
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.check_chip_id = sia8152s_check_chip_id,
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.set_xfilter = NULL,
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.chip_on = sia8152s_chip_on,
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.chip_off = sia8152s_chip_off,
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.get_chip_en = sia8152s_get_chip_en,
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.set_pvdd_limit = sia8152s_set_pvdd_limit,
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.check_trimming = sia8152s_check_trimming,
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};
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