threeeye
bc1d038eac
Squashed backup commit (no shallow-clone history issues) of xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2 branch, upstream commit 9eece662e) plus all fixes applied to get everpal_defconfig building clean against a modern (GCC 15.2.0) toolchain -- see the previous commit message on the lineage-23.2 branch (also in this repo history is not available here since this is a squashed snapshot; full incremental history lives in the local DL380 checkout and the upstream GitHub remote). Upstream: https://github.com/xiaomi-mt6833-dev/kernel_xiaomi_mt6833 (lineage-23.2)
773 lines
20 KiB
C
773 lines
20 KiB
C
/*
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* mt6392-codec.c -- MT6392 ALSA SoC codec driver
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*
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* Copyright (c) 2016 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <sound/soc.h>
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#include <sound/tlv.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include "mt6392-codec.h"
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#define MT6392_CODEC_NAME "mt6392-codec"
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enum mt6392_speaker_mode {
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MT6392_CLASS_D = 0,
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MT6392_CLASS_AB,
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};
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struct mt6392_codec_priv {
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struct snd_soc_codec *codec;
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struct regmap *regmap;
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uint32_t speaker_mode;
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uint32_t spk_amp_gain;
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uint16_t spk_trim_offset;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *debugfs;
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#endif
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};
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/*
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* Class D: has HW Trim mode and SW Trim mode
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* Class AB: use the trim offset derived from Class D HW Trim
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*
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* The option used to choose the trim mode of Class D
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*/
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#define USE_HW_TRIM_CLASS_D
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/* Int Spk Amp Playback Volume
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* {mute, 0, 4, 5, 6, 7, 8, ..., 17} dB
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*/
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static const unsigned int int_spk_amp_gain_tlv[] = {
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TLV_DB_RANGE_HEAD(3),
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0, 0, TLV_DB_SCALE_ITEM(0, 0, 1),
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1, 1, TLV_DB_SCALE_ITEM(0, 0, 0),
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2, 15, TLV_DB_SCALE_ITEM(400, 100, 0),
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};
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/* Audio_Speaker_PGA_gain
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* {mute, 0, 4, 5, 6, 7, 8, ..., 17} dB
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*/
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static const char *const int_spk_amp_gain_text[] = {
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"MUTE", "+0dB", "+4dB", "+5dB",
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"+6dB", "+7dB", "+8dB", "+9dB",
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"+10dB", "+11dB", "+12dB", "+13dB",
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"+14dB", "+15dB", "+16dB", "+17dB",
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};
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static const struct soc_enum int_spk_amp_gain_enum =
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SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(int_spk_amp_gain_text),
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int_spk_amp_gain_text);
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static int int_spk_amp_gain_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct mt6392_codec_priv *codec_data =
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snd_soc_component_get_drvdata(component);
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uint32_t value = 0;
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value = codec_data->spk_amp_gain;
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ucontrol->value.integer.value[0] = value;
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return 0;
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}
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static int int_spk_amp_gain_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct mt6392_codec_priv *codec_data =
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snd_soc_component_get_drvdata(component);
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struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
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uint32_t value = ucontrol->value.integer.value[0];
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if (value >= e->items)
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return -EINVAL;
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snd_soc_update_bits(codec_data->codec, SPK_CON9,
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GENMASK(11, 8), value << 8);
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codec_data->spk_amp_gain = value;
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dev_dbg(codec_data->codec->dev, "%s value = %u\n",
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__func__, value);
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return 0;
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}
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static int int_spk_amp_gain_put_volsw(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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int ret = 0;
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct mt6392_codec_priv *codec_data =
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snd_soc_component_get_drvdata(component);
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ret = snd_soc_put_volsw(kcontrol, ucontrol);
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if (ret < 0)
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return ret;
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codec_data->spk_amp_gain = ucontrol->value.integer.value[0];
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return 0;
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}
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/* Internal speaker mode (AB/D) */
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static const char * const int_spk_amp_mode_texts[] = {
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"Class D",
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"Class AB",
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};
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static SOC_ENUM_SINGLE_EXT_DECL(mt6392_speaker_mode_enum,
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int_spk_amp_mode_texts);
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static int mt6392_spk_mode_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct mt6392_codec_priv *codec_data =
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snd_soc_component_get_drvdata(component);
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ucontrol->value.integer.value[0] = codec_data->speaker_mode;
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return 0;
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}
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static int mt6392_spk_mode_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct mt6392_codec_priv *codec_data =
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snd_soc_component_get_drvdata(component);
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int ret = 0;
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uint32_t mode = ucontrol->value.integer.value[0];
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switch (mode) {
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case MT6392_CLASS_D:
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case MT6392_CLASS_AB:
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codec_data->speaker_mode = ucontrol->value.integer.value[0];
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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/* Check OC Flag */
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static const char *const mt6392_speaker_oc_flag_texts[] = {
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"NoOverCurrent",
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"OverCurrent"
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};
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static SOC_ENUM_SINGLE_EXT_DECL(mt6392_speaker_oc_flag_enum,
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mt6392_speaker_oc_flag_texts);
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static int mt6392_speaker_oc_flag_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct mt6392_codec_priv *codec_data =
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snd_soc_component_get_drvdata(component);
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uint32_t reg_value = snd_soc_read(codec_data->codec, SPK_CON6);
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if (codec_data->speaker_mode == MT6392_CLASS_AB)
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ucontrol->value.integer.value[0] =
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(reg_value & BIT(15)) ? 1 : 0;
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else
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ucontrol->value.integer.value[0] =
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(reg_value & BIT(14)) ? 1 : 0;
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return 0;
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}
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static void mt6392_codec_get_spk_trim_offset(struct snd_soc_codec *codec)
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{
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struct mt6392_codec_priv *codec_data =
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snd_soc_codec_get_drvdata(codec);
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/* turn on spk (class D) and hw trim */
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snd_soc_update_bits(codec, TOP_CKPDN1_CLR, 0x000E, 0x000E);
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snd_soc_update_bits(codec, SPK_CON7, 0xFFFF, 0x48F4);
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snd_soc_update_bits(codec, SPK_CON11, 0xFFFF, 0x0055);
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snd_soc_update_bits(codec, SPK_CON9, 0xF0FF, 0x2018);
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snd_soc_update_bits(codec, SPK_CON2, 0xFFFF, 0x0414);
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snd_soc_update_bits(codec, SPK_CON0, 0xFFFF, 0x3409);
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usleep_range(20000, 21000);
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/* save trim offset */
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codec_data->spk_trim_offset =
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snd_soc_read(codec, SPK_CON1) & GENMASK(4, 0);
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/* turn off trim */
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snd_soc_update_bits(codec, SPK_CON0, 0xFFFF, 0x3401);
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snd_soc_update_bits(codec, SPK_CON9, 0xF0FF, 0x2000);
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usleep_range(2000, 3000);
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/* turn off spk */
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snd_soc_update_bits(codec, SPK_CON12, 0xFFFF, 0x0000);
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snd_soc_update_bits(codec, SPK_CON0, 0xFFFF, 0x3400);
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snd_soc_update_bits(codec, TOP_CKPDN1_CLR, 0x000E, 0x0000);
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}
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static void mt6392_int_spk_on_with_trim(struct snd_soc_codec *codec)
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{
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#if defined(USE_HW_TRIM_CLASS_D)
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/* turn on spk (class D) and hw trim */
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snd_soc_update_bits(codec, TOP_CKPDN1_CLR, 0x000E, 0x000E);
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snd_soc_update_bits(codec, SPK_CON7, 0xFFFF, 0x48F4);
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snd_soc_update_bits(codec, SPK_CON11, 0xFFFF, 0x0055);
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snd_soc_update_bits(codec, SPK_CON9, 0xF0FF, 0x2018);
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snd_soc_update_bits(codec, SPK_CON2, 0xFFFF, 0x0414);
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snd_soc_update_bits(codec, SPK_CON0, 0xFFFF, 0x3409);
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usleep_range(20000, 21000);
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/* turn off trim */
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snd_soc_update_bits(codec, SPK_CON0, 0xFFFF, 0x3401);
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snd_soc_update_bits(codec, SPK_CON9, 0xF0FF, 0x2000);
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#else
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struct mt6392_codec_priv *codec_data =
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snd_soc_codec_get_drvdata(codec);
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/* turn on spk (class D) */
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snd_soc_update_bits(codec, TOP_CKPDN1_CLR, 0x000E, 0x000E);
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snd_soc_update_bits(codec, SPK_CON7, 0xFFFF, 0x48F4);
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snd_soc_update_bits(codec, SPK_CON2, 0xFFFF, 0x0414);
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snd_soc_update_bits(codec, SPK_CON0, 0xFFFF, 0x3001);
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snd_soc_update_bits(codec, SPK_CON9, 0xF0FF, 0x2000);
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/* enable sw trim */
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snd_soc_update_bits(codec, SPK_CON12, 0xFFFF, 0x0009);
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snd_soc_update_bits(codec, SPK_CON12, 0xFFFF, 0x0001);
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snd_soc_update_bits(codec, SPK_CON12, 0xFFFF, 0x0283);
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snd_soc_update_bits(codec, SPK_CON12, 0xFFFF, 0x0281);
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snd_soc_update_bits(codec, SPK_CON12, 0xFFFF, 0x2A81);
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snd_soc_update_bits(codec, SPK_CON1, 0xFFFF, 0x6000);
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/* class D and class AB use the same trim offset value */
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snd_soc_update_bits(codec, SPK_CON1,
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GENMASK(12, 8), (codec_data->spk_trim_offset << 8));
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/* trim stop */
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snd_soc_update_bits(codec, SPK_CON12, 0xFFFF, 0xAA81);
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#endif
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usleep_range(2000, 3000);
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}
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static int mt6392_int_spk_turn_on(struct snd_soc_codec *codec)
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{
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struct mt6392_codec_priv *codec_data =
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snd_soc_codec_get_drvdata(codec);
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int ret = 0;
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dev_dbg(codec->dev, "%s\n", __func__);
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switch (codec_data->speaker_mode) {
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case MT6392_CLASS_D:
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mt6392_int_spk_on_with_trim(codec);
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break;
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case MT6392_CLASS_AB:
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snd_soc_update_bits(codec, TOP_CKPDN1_CLR, 0x000E, 0x000E);
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snd_soc_update_bits(codec, SPK_CON7, 0xFFFF, 0x48F4);
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snd_soc_update_bits(codec, SPK_CON2, 0xFFFF, 0x0414);
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snd_soc_update_bits(codec, SPK_CON0, 0xFFFF, 0x3005);
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snd_soc_update_bits(codec, SPK_CON9, 0xF0FF, 0x2000);
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snd_soc_update_bits(codec, SPK_CON1, 0xFFFF, 0x6000);
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/* class D and class AB use the same trim offset value */
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snd_soc_update_bits(codec, SPK_CON1,
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GENMASK(12, 8), (codec_data->spk_trim_offset << 8));
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usleep_range(2000, 3000);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int mt6392_int_spk_turn_off(struct snd_soc_codec *codec)
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{
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struct mt6392_codec_priv *codec_data =
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snd_soc_codec_get_drvdata(codec);
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int ret = 0;
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dev_dbg(codec->dev, "%s\n", __func__);
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switch (codec_data->speaker_mode) {
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case MT6392_CLASS_D:
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snd_soc_update_bits(codec, SPK_CON12, 0xFFFF, 0x0000);
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snd_soc_update_bits(codec, SPK_CON0, 0xFFFF, 0x3400);
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snd_soc_update_bits(codec, TOP_CKPDN1_CLR, 0x000E, 0x0000);
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break;
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case MT6392_CLASS_AB:
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snd_soc_update_bits(codec, SPK_CON0, 0xFFFF, 0x3404);
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snd_soc_update_bits(codec, TOP_CKPDN1_CLR, 0x000E, 0x0000);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int mt6392_int_spk_amp_wevent(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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{
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struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
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dev_dbg(codec->dev, "%s, event %d\n", __func__, event);
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switch (event) {
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case SND_SOC_DAPM_POST_PMU:
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mt6392_int_spk_turn_on(codec);
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break;
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case SND_SOC_DAPM_PRE_PMD:
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mt6392_int_spk_turn_off(codec);
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break;
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default:
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break;
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}
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return 0;
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}
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/* Int Spk Amp Switch */
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static int mt6392_codec_int_spk_amp_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct mt6392_codec_priv *codec_data =
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snd_soc_component_get_drvdata(component);
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struct snd_soc_codec *codec = codec_data->codec;
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long int_spk_amp_en = snd_soc_read(codec, SPK_CON0) & BIT(0);
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ucontrol->value.integer.value[0] = int_spk_amp_en;
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return 0;
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}
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static int mt6392_codec_int_spk_amp_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
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struct mt6392_codec_priv *codec_data =
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snd_soc_component_get_drvdata(component);
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struct snd_soc_codec *codec = codec_data->codec;
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long int_spk_amp_en = ucontrol->value.integer.value[0];
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if (int_spk_amp_en)
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mt6392_int_spk_turn_on(codec);
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else
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mt6392_int_spk_turn_off(codec);
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return 0;
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}
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static const struct snd_kcontrol_new mt6392_codec_controls[] = {
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/* Internal speaker PGA gain control */
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SOC_SINGLE_EXT_TLV("Int Spk Amp Playback Volume",
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SPK_CON9, 8, 15, 0,
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snd_soc_get_volsw,
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int_spk_amp_gain_put_volsw,
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int_spk_amp_gain_tlv),
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/* Audio_Speaker_PGA_gain */
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SOC_ENUM_EXT("Audio_Speaker_PGA_gain",
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int_spk_amp_gain_enum,
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int_spk_amp_gain_get,
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int_spk_amp_gain_put),
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/* Internal speaker mode (AB/D) */
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SOC_ENUM_EXT("Int Spk Amp Mode", mt6392_speaker_mode_enum,
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mt6392_spk_mode_get, mt6392_spk_mode_put),
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/* Check OC Flag */
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SOC_ENUM_EXT("Speaker_OC_Flag", mt6392_speaker_oc_flag_enum,
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mt6392_speaker_oc_flag_get, NULL),
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/* Int Spk Amp Switch */
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SOC_SINGLE_BOOL_EXT("Int Spk Amp Switch",
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0,
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mt6392_codec_int_spk_amp_get,
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mt6392_codec_int_spk_amp_put),
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};
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static const struct snd_soc_dapm_widget mt6392_codec_dapm_widgets[] = {
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SND_SOC_DAPM_AIF_IN("MT6392 AIF RX", "MT6392 Playback", 0,
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SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_SPK("Int Spk Amp", mt6392_int_spk_amp_wevent),
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};
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static const struct snd_soc_dapm_route mt6392_codec_dapm_routes[] = {
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{"Int Spk Amp", NULL, "MT6392 AIF RX"},
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};
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static int module_reg_read(void *context, unsigned int reg, unsigned int *val,
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unsigned int offset)
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{
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struct mt6392_codec_priv *codec_data =
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(struct mt6392_codec_priv *) context;
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int ret = 0;
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if (!(codec_data && codec_data->regmap))
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return -1;
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ret = regmap_read(codec_data->regmap,
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(reg & (~offset)), val);
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return ret;
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}
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static int module_reg_write(void *context, unsigned int reg, unsigned int val,
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unsigned int offset)
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{
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struct mt6392_codec_priv *codec_data =
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(struct mt6392_codec_priv *) context;
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int ret = 0;
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if (!(codec_data && codec_data->regmap))
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return -1;
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ret = regmap_write(codec_data->regmap,
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(reg & (~offset)), val);
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return ret;
|
|
}
|
|
|
|
static bool reg_is_in_pmic(unsigned int reg)
|
|
{
|
|
if (reg & PMIC_OFFSET)
|
|
return true;
|
|
else
|
|
return false;
|
|
}
|
|
|
|
/* regmap functions */
|
|
static int codec_reg_read(void *context,
|
|
unsigned int reg, unsigned int *val)
|
|
{
|
|
unsigned int offset;
|
|
|
|
if (reg_is_in_pmic(reg))
|
|
offset = PMIC_OFFSET;
|
|
else
|
|
return -1;
|
|
|
|
return module_reg_read(context, reg, val, offset);
|
|
}
|
|
|
|
static int codec_reg_write(void *context,
|
|
unsigned int reg, unsigned int val)
|
|
{
|
|
unsigned int offset;
|
|
|
|
if (reg_is_in_pmic(reg))
|
|
offset = PMIC_OFFSET;
|
|
else
|
|
return -1;
|
|
|
|
return module_reg_write(context, reg, val, offset);
|
|
}
|
|
|
|
static void codec_regmap_lock(void *lock_arg)
|
|
{
|
|
}
|
|
|
|
static void codec_regmap_unlock(void *lock_arg)
|
|
{
|
|
}
|
|
|
|
static struct regmap_config mt6392_codec_regmap_config = {
|
|
.reg_bits = 16,
|
|
.val_bits = 16,
|
|
.reg_read = codec_reg_read,
|
|
.reg_write = codec_reg_write,
|
|
.lock = codec_regmap_lock,
|
|
.unlock = codec_regmap_unlock,
|
|
.cache_type = REGCACHE_NONE,
|
|
};
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
struct mt6392_codec_reg_attr {
|
|
uint32_t offset;
|
|
char *name;
|
|
};
|
|
|
|
#define DUMP_REG_ENTRY(reg) {reg, #reg}
|
|
|
|
static const struct mt6392_codec_reg_attr mt6392_codec_dump_reg_list[] = {
|
|
DUMP_REG_ENTRY(SPK_CON0),
|
|
DUMP_REG_ENTRY(SPK_CON1),
|
|
DUMP_REG_ENTRY(SPK_CON2),
|
|
DUMP_REG_ENTRY(SPK_CON3),
|
|
DUMP_REG_ENTRY(SPK_CON4),
|
|
DUMP_REG_ENTRY(SPK_CON5),
|
|
DUMP_REG_ENTRY(SPK_CON6),
|
|
DUMP_REG_ENTRY(SPK_CON7),
|
|
DUMP_REG_ENTRY(SPK_CON8),
|
|
DUMP_REG_ENTRY(SPK_CON9),
|
|
DUMP_REG_ENTRY(SPK_CON10),
|
|
DUMP_REG_ENTRY(SPK_CON11),
|
|
DUMP_REG_ENTRY(SPK_CON12),
|
|
};
|
|
|
|
static ssize_t mt6392_codec_debug_read(struct file *file,
|
|
char __user *user_buf,
|
|
size_t count, loff_t *pos)
|
|
{
|
|
struct mt6392_codec_priv *codec_data = file->private_data;
|
|
ssize_t ret, i;
|
|
char *buf;
|
|
int n = 0;
|
|
|
|
if (*pos < 0 || !count)
|
|
return -EINVAL;
|
|
|
|
buf = kmalloc(count, GFP_KERNEL);
|
|
if (!buf)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mt6392_codec_dump_reg_list); i++) {
|
|
n += scnprintf(buf + n, count - n, "%s = 0x%x\n",
|
|
mt6392_codec_dump_reg_list[i].name,
|
|
snd_soc_read(codec_data->codec,
|
|
mt6392_codec_dump_reg_list[i].offset));
|
|
}
|
|
|
|
ret = simple_read_from_buffer(user_buf, count, pos, buf, n);
|
|
|
|
kfree(buf);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct file_operations mt6392_codec_debug_ops = {
|
|
.open = simple_open,
|
|
.read = mt6392_codec_debug_read,
|
|
.llseek = default_llseek,
|
|
};
|
|
#endif
|
|
|
|
static void mt6392_codec_init_regs(struct mt6392_codec_priv *codec_data)
|
|
{
|
|
struct snd_soc_codec *codec = codec_data->codec;
|
|
|
|
dev_dbg(codec->dev, "%s\n", __func__);
|
|
|
|
/* default PGA gain: 12dB */
|
|
codec_data->spk_amp_gain = 0xA;
|
|
snd_soc_update_bits(codec, SPK_CON9,
|
|
GENMASK(11, 8), (codec_data->spk_amp_gain) << 8);
|
|
}
|
|
|
|
static struct regmap *mt6392_codec_get_regmap_from_dt(const char *phandle_name,
|
|
struct mt6392_codec_priv *codec_data)
|
|
{
|
|
struct device_node *self_node = NULL, *node = NULL;
|
|
struct platform_device *platdev = NULL;
|
|
struct device *dev = codec_data->codec->dev;
|
|
struct regmap *regmap = NULL;
|
|
|
|
self_node = of_find_compatible_node(NULL, NULL,
|
|
"mediatek," MT6392_CODEC_NAME);
|
|
if (!self_node) {
|
|
dev_dbg(dev, "%s failed to find %s node\n",
|
|
__func__, MT6392_CODEC_NAME);
|
|
return NULL;
|
|
}
|
|
dev_dbg(dev, "%s found %s node\n", __func__, MT6392_CODEC_NAME);
|
|
|
|
node = of_parse_phandle(self_node, phandle_name, 0);
|
|
if (!node) {
|
|
dev_dbg(dev, "%s failed to find %s node\n",
|
|
__func__, phandle_name);
|
|
return NULL;
|
|
}
|
|
dev_dbg(dev, "%s found %s\n", __func__, phandle_name);
|
|
|
|
platdev = of_find_device_by_node(node);
|
|
if (!platdev) {
|
|
dev_dbg(dev, "%s failed to get platform device of %s\n",
|
|
__func__, phandle_name);
|
|
return NULL;
|
|
}
|
|
dev_dbg(dev, "%s found platform device of %s\n",
|
|
__func__, phandle_name);
|
|
|
|
regmap = dev_get_regmap(&platdev->dev, NULL);
|
|
if (regmap) {
|
|
dev_dbg(dev, "%s found regmap of %s\n", __func__, phandle_name);
|
|
return regmap;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static int mt6392_codec_parse_dt(struct snd_soc_codec *codec)
|
|
{
|
|
struct mt6392_codec_priv *codec_data =
|
|
snd_soc_codec_get_drvdata(codec);
|
|
struct device *dev = codec->dev;
|
|
int ret = 0;
|
|
|
|
codec_data->regmap = mt6392_codec_get_regmap_from_dt(
|
|
"mediatek,pwrap-regmap",
|
|
codec_data);
|
|
if (!codec_data->regmap) {
|
|
dev_dbg(dev, "%s failed to get %s\n",
|
|
__func__, "mediatek,pwrap-regmap");
|
|
devm_kfree(dev, codec_data);
|
|
ret = -EPROBE_DEFER;
|
|
return ret;
|
|
}
|
|
|
|
ret = of_property_read_u32(dev->of_node, "mediatek,speaker-mode",
|
|
&codec_data->speaker_mode);
|
|
if (ret) {
|
|
dev_dbg(dev, "%s fail to read speaker-mode in node %s\n",
|
|
__func__, dev->of_node->full_name);
|
|
codec_data->speaker_mode = MT6392_CLASS_D;
|
|
} else if (codec_data->speaker_mode != MT6392_CLASS_D &&
|
|
codec_data->speaker_mode != MT6392_CLASS_AB) {
|
|
codec_data->speaker_mode = MT6392_CLASS_D;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
#define MT6392_CODEC_DL_RATES SNDRV_PCM_RATE_8000_48000
|
|
|
|
static struct snd_soc_dai_driver mt6392_codec_dai = {
|
|
.name = "mt6392-codec-dai",
|
|
.playback = {
|
|
.stream_name = "MT6392 Playback",
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = MT6392_CODEC_DL_RATES,
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE,
|
|
},
|
|
};
|
|
|
|
static int mt6392_codec_probe(struct snd_soc_codec *codec)
|
|
{
|
|
struct mt6392_codec_priv *codec_data =
|
|
snd_soc_codec_get_drvdata(codec);
|
|
int ret = 0;
|
|
|
|
codec_data->codec = codec;
|
|
|
|
mt6392_codec_parse_dt(codec);
|
|
|
|
mt6392_codec_init_regs(codec_data);
|
|
|
|
mt6392_codec_get_spk_trim_offset(codec);
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
codec_data->debugfs = debugfs_create_file("mt6392_codec_regs",
|
|
S_IFREG | 0444,
|
|
NULL, codec_data, &mt6392_codec_debug_ops);
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
static int mt6392_codec_remove(struct snd_soc_codec *codec)
|
|
{
|
|
#ifdef CONFIG_DEBUG_FS
|
|
struct mt6392_codec_priv *codec_data =
|
|
snd_soc_codec_get_drvdata(codec);
|
|
debugfs_remove(codec_data->debugfs);
|
|
#endif
|
|
dev_dbg(codec->dev, "%s\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
static struct snd_soc_codec_driver mt6392_codec_driver = {
|
|
.probe = mt6392_codec_probe,
|
|
.remove = mt6392_codec_remove,
|
|
|
|
.component_driver = {
|
|
.controls = mt6392_codec_controls,
|
|
.num_controls = ARRAY_SIZE(mt6392_codec_controls),
|
|
.dapm_widgets = mt6392_codec_dapm_widgets,
|
|
.num_dapm_widgets = ARRAY_SIZE(mt6392_codec_dapm_widgets),
|
|
.dapm_routes = mt6392_codec_dapm_routes,
|
|
.num_dapm_routes = ARRAY_SIZE(mt6392_codec_dapm_routes),
|
|
},
|
|
};
|
|
|
|
static int mt6392_codec_dev_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct mt6392_codec_priv *codec_data = NULL;
|
|
|
|
dev_dbg(dev, "%s dev name %s\n", __func__, dev_name(dev));
|
|
|
|
if (dev->of_node) {
|
|
dev_set_name(dev, "%s", MT6392_CODEC_NAME);
|
|
dev_dbg(dev, "%s set dev name %s\n", __func__, dev_name(dev));
|
|
}
|
|
|
|
codec_data = devm_kzalloc(dev,
|
|
sizeof(struct mt6392_codec_priv), GFP_KERNEL);
|
|
pdev->name = pdev->dev.kobj.name;
|
|
|
|
if (!codec_data)
|
|
return -ENOMEM;
|
|
|
|
dev_set_drvdata(dev, codec_data);
|
|
|
|
/* get regmap of codec */
|
|
codec_data->regmap = devm_regmap_init(dev, NULL, codec_data,
|
|
&mt6392_codec_regmap_config);
|
|
if (IS_ERR(codec_data->regmap)) {
|
|
dev_dbg(dev, "%s failed to get regmap of codec\n", __func__);
|
|
devm_kfree(dev, codec_data);
|
|
codec_data->regmap = NULL;
|
|
return -EINVAL;
|
|
}
|
|
|
|
return snd_soc_register_codec(dev,
|
|
&mt6392_codec_driver, &mt6392_codec_dai, 1);
|
|
}
|
|
|
|
static int mt6392_codec_dev_remove(struct platform_device *pdev)
|
|
{
|
|
snd_soc_unregister_codec(&pdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id mt6392_codec_dt_match[] = {
|
|
{.compatible = "mediatek," MT6392_CODEC_NAME,},
|
|
{}
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, mt6392_codec_dt_match);
|
|
|
|
static struct platform_driver mt6392_codec_device_driver = {
|
|
.driver = {
|
|
.name = MT6392_CODEC_NAME,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = mt6392_codec_dt_match,
|
|
},
|
|
.probe = mt6392_codec_dev_probe,
|
|
.remove = mt6392_codec_dev_remove,
|
|
};
|
|
|
|
module_platform_driver(mt6392_codec_device_driver);
|
|
|
|
/* Module information */
|
|
MODULE_DESCRIPTION("ASoC MT6392 driver");
|
|
MODULE_LICENSE("GPL v2");
|